Memory devices and method of forming the same

Patent metadata

Field	Value
Publication number	US-11818969-B2
Application number	US-202017096950-A
Country	US
Kind code	B2
Filing date	Nov 13, 2020
Priority date	Nov 13, 2020
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

The disclosed subject matter relates generally to memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a first electrode having tapered sides that converge at a top of the first electrode, a dielectric layer disposed on and conforming to the tapered sides of the first electrode, a resistive layer in contact with the top of the first electrode and the dielectric layer, and a second electrode disposed on the resistive layer.

First claim

What is claimed is:

1. A memory device comprising:
a first electrode having tapered sides that converge at a top of the first electrode;
a dielectric layer disposed on and conforming to the tapered sides of the first electrode;
a resistive layer in contact with the top of the first electrode and the dielectric layer; and
a second electrode disposed on the resistive layer, wherein the resistive layer conforms to a bottom and side surfaces of the second electrode.

2. The device of claim 1 , wherein the dielectric layer has an upper surface that is substantially coplanar with the top of the first electrode.

3. The device of claim 1 , wherein the tapered sides of the first electrode converge to form a substantially pointed tip at the top of the first electrode.

4. The device of claim 1 , wherein the tapered sides of the first electrode converge to form a substantially rounded tip at the top of the first electrode.

5. The device of claim 1 , wherein the top of the first electrode is an edge with a length.

6. The device of claim 1 , further comprising:
a first inter-metal dielectric region comprising a first interconnect structure, wherein the first electrode is disposed on the first interconnect structure; and
a second inter-metal dielectric region above the first inter-metal dielectric region, the second inter-metal dielectric region comprising a second interconnect structure, wherein the second interconnect structure is disposed on the second electrode.

7. The device of claim 6 , further comprising mask elements in the second inter-metal dielectric region, wherein the second electrode is between the mask elements and the mask elements have upper surfaces that are substantially coplanar with an upper surface of the second electrode.

8. The device of claim 1 , wherein the first electrode has a bottom surface with an elliptical shape.

9. The device of claim 8 , wherein the first electrode has a conical geometry.

10. The device of claim 1 , wherein the first electrode has a bottom surface with a polygonal shape.

11. The device of claim 10 , wherein the first electrode has a pyramidal geometry.

12. The device of claim 10 , wherein the first electrode has a triangular cross sectional shape.

13. A method of forming a memory device comprising:
forming a first electrode having tapered sides that converge at a top of the first electrode;
forming a dielectric layer on and conforming to the tapered sides of the first electrode;
forming a resistive layer to contact the top of the first electrode and the dielectric layer; and
forming a second electrode on the resistive layer, wherein the resistive layer conforms to a bottom and side surfaces of the second electrode.

14. A memory device comprising:
a first electrode having tapered sides that converge at a top of the first electrode, wherein the top of the first electrode is an edge with a length;
a dielectric layer disposed on and conforming to the tapered sides of the first electrode;
a resistive layer in contact with the top of the first electrode and the dielectric layer; and
a second electrode disposed on the resistive layer.

15. The device of claim 14 , wherein the resistive layer conforms to a bottom and side surfaces of the second electrode.

16. The device of claim 15 , further comprising:
a first inter-metal dielectric region comprising a first interconnect structure, wherein the first electrode is disposed on the first interconnect structure; and
a second inter-metal dielectric region above the first inter-metal dielectric region, the second inter-metal dielectric region comprising a second interconnect structure, wherein the second interconnect structure is disposed on the second electrode.

17. The device of claim 16 , further comprising mask elements in the second inter-metal dielectric region, wherein the second electrode is between the mask elements and the mask elements have upper surfaces that are substantially coplanar with an upper surface of the second electrode.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Sun Jianxun
• Tan Juan Boon
• Chen Tupei

Classifications

• H10B63/00

  Resistance change memory devices, e.g. resistive RAM [ReRAM] devices · CPC title

• H10N70/841 Primary

  Electrodes · CPC title

• H10N70/021

  Formation of switching materials, e.g. deposition of layers · CPC title

• H10N70/063

  by etching of pre-deposited switching material layers, e.g. lithography · CPC title

• H10N70/8833

  Binary metal oxides, e.g. TaOx · CPC title