Termination structures with reduced dynamic output capacitance loss

Patent metadata

Field	Value
Publication number	US-11817478-B2
Application number	US-202017247796-A
Country	US
Kind code	B2
Filing date	Dec 23, 2020
Priority date	Dec 23, 2020
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

In a general aspect, a semiconductor device can include a substrate of a first conductivity type, an active region disposed in the substrate, and a termination region disposed in the substrate adjacent to the active region. The termination region can include a junction termination extension (JTE) of a second conductivity type, where the second conductivity type is opposite the first conductivity type. The JTE can have a first depletion stopper region disposed in an upper portion of the JTE, a second depletion stopper region disposed in a lower portion of the JTE, and a high carrier mobility region disposed between the first depletion stopper region and the second depletion stopper region.

First claim

What is claimed is:

1. A semiconductor device:
a substrate of a first conductivity type;
an active region disposed in the substrate, the active region including at least one active device; and
a termination region disposed in the substrate adjacent to the active region, the termination region excluding an active device, the termination region including a junction termination extension (JTE) of a second conductivity type, the second conductivity type being opposite the first conductivity type, the JTE having:
a first depletion stopper region disposed in an upper portion of the JTE;
a second depletion stopper region disposed in a lower portion of the JTE; and
a high carrier mobility region disposed between the first depletion stopper region and the second depletion stopper region, the high carrier mobility region having a constant doping region extending over a range of depths of the high carrier mobility region in the substrate, the high carrier mobility region having a carrier mobility that is greater than respective carrier mobilities of the first depletion stopper region and the second depletion stopper region.

2. The semiconductor device of claim 1 , wherein:
the first depletion stopper region has a first doping concentration;
the second depletion stopper region has a second doping concentration; and
the high carrier mobility region has a third doping concentration, the third doping concentration being less than the first doping concentration, and less than the second doping concentration.

3. The semiconductor device of claim 2 , wherein the first doping concentration and the second doping concentration are a same doping concentration.

4. The semiconductor device of claim 2 , wherein the first doping concentration is different than the second doping concentration.

5. The semiconductor device of claim 2 , wherein:
the first doping concentration is a first average doping concentration;
the second doping concentration is a second average doping concentration; and
the third doping concentration is a third average doping concentration.

6. The semiconductor device of claim 1 , wherein:
the substrate is a silicon carbide substrate;
the first conductivity type is n-type; and
the second conductivity type is p-type.

7. The semiconductor device of claim 1 , wherein the JTE is a first JTE and the high carrier mobility region is a first high carrier mobility region, the termination region further including:
a second JTE of the second conductivity type disposed in the substrate adjacent to the first JTE, the second JTE including:
a third depletion stopper region disposed in an upper portion of the second JTE;
a fourth depletion stopper region disposed in a lower portion of the second JTE; and
a second high carrier mobility region disposed between the third depletion stopper region and the fourth depletion stopper region.

8. The semiconductor device of claim 7 , wherein:
the first JTE extends from a surface of the substrate to a first depth in the substrate; and
the second JTE extends from the surface of the substrate to a second depth in the substrate, the second depth being less than the first depth.

9. The semiconductor device of claim 7 , wherein the first high carrier mobility region and the second high carrier mobility region are aligned along a common longitudinal axis.

10. The semiconductor device of claim 7 , wherein:
the first JTE includes a first dopant impurity dose; and
the second JTE includes a second dopant impurity dose, the second dopant impurity dose being less than the first dopant impurity dose.

11. The semiconductor device of claim 1 , wherein the high carrier mobility region is a first high carrier mobility region, the termination region further including:
at least one floating ring of the second conductivity type disposed in the substrate and laterally spaced from the JTE, the JTE being disposed between the active region and the at least one floating ring,
a floating ring of the at least one floating ring having:
a third depletion stopper region disposed in an upper portion of the floating ring;
a fourth depletion stopper region disposed in a lower portion of the floating ring; and
a second high carrier mobility region disposed between the third depletion stopper region and the fourth depletion stopper region.

12. The semiconductor device of claim 11 , wherein the first high carrier mobility region and the second high carrier mobility region are aligned along a common longitudinal axis.

13. The semiconductor device of claim 9 , wherein:
the first JTE has a first width along the common longitudinal axis; and
the second JTE has a second width along the common longitudinal axis, the second width being less than the first width.

14. The semiconductor device of claim 1 , wherein the active region includes at least one of:
a power diode; or
a power transistor.

15. A semiconductor device:
a substrate of a first conductivity type;
an active region disposed in the substrate, the active region including at least one active device; and
a termination region disposed in the substrate adjacent to the active region, the termination region excluding an active device, the termination region including a junction termination extension (JTE) of a second conductivity type, the second conductivity type being opposite the first conductivity type, the JTE having:
a first depletion stopper region extending from a surface of the substrate to a first depth in the substrate;
a high carrier mobility region extending from the first depth in the substrate to a second depth in the substrate, the second depth being greater than the first depth, the high carrier mobility region having a constant doping region extending over a range of depths between the first depth and the second depth; and
a second depletion stopper region extending from the second depth in the substrate to a third depth in the substrate, the third depth being greater than the second depth,
the high carrier mobility region having a carrier mobility that is greater than respective carrier mobilities of the first depletion stopper region and the second depletion stopper region.

16. The semiconductor device of claim 15 , wherein:
the first depletion stopper region includes a first amount of dopant of the second conductivity type;
the high carrier mobility region includes a second amount of dopant of the second conductivity type, the second amount of dopant being less than the first amount of dopant; and
the second depletion stopper region includes a third amount of dopant of the second conductivity type, the third amount of dopant being greater than the second amount of dopant.

17. The semiconductor device of claim 15 , wherein a difference between the second depth and the first depth is:
greater than the first depth; and
greater than a difference between the third depth and the second depth.

18. A semiconductor device:
a substrate including:
a heavily-doped n-type silicon carbide substrate; and
a lightly-doped n-type silicon carbide epitaxial layer disposed on the heavily-doped n-type silicon carbide substrate;

an active region disposed in the lightly-doped n-type silicon carbide epitaxial layer, the active region including at least one of:
a power diode; or
a power n-channel metal-oxide semiconductor field-effect transistor (MOSFET); and

a termination region disposed in the lightly-doped n-type silicon carbide epitaxial layer adjacent to the active region, the termination region excluding an active device, the termination reg

Assignees

• Semiconductor Components Ind Llc

Inventors

• Roig-Guitart Jaume
• Allerstam Fredrik
• Neyer Thomas
• Konstantinov Andrei
• Domeij Martin
• Lim Jangkwon

Classifications

• H10D12/031

  of IGBTs · CPC title

• H10D8/051

  of Schottky diodes · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/106 Primary

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title

• H10D62/107 Primary

  Buried supplementary regions, e.g. buried guard rings  (multi-RESURF H10D62/111) · CPC title