Diode and method of manufacturing diode

Patent metadata

Field	Value
Publication number	US-2016300960-A1
Application number	US-201615092929-A
Country	US
Kind code	A1
Filing date	Apr 7, 2016
Priority date	Apr 9, 2015
Publication date	Oct 13, 2016
Grant date	—

Abstract

A diode is provided with a semiconductor substrate; an anode electrode located on a front surface of the semiconductor substrate; and a cathode electrode located on a rear surface of the semiconductor substrate. Each of the p-type contact regions includes: a first region being in contact with the anode electrode; a second region located on the rear surface side of the first region, having a p-type impurity density lower than a p-type impurity density in the first region; and a third region located on the rear surface side of the second region and having a p-type impurity density lower than the p-type impurity density in the second region. A thickness of the second region is thicker than a thickness of the first region.

First claim

What is claimed is:

1 . A diode comprising:
a semiconductor substrate; an anode electrode located on a front surface of the semiconductor substrate; and a cathode electrode located on a rear surface of the semiconductor substrate, wherein the semiconductor substrate comprises: a plurality of p-type contact regions being in contact with the anode electrode; an n-type contact region located between the adjacent p-type contact regions and being in contact with the anode electrode; and an n-type cathode region located on a rear surface side of the p-type contact regions and the n-type contact region and being in contact with the cathode electrode, each of the p-type contact regions comprises: a first region being in contact with the anode electrode; a second region located on the rear surface side of the first region, having a p-type impurity density lower than a p-type impurity density in the first region, wherein the p-type impurity density in the second region is distributed within a range from minus 30% to plus 30% with respect to an average value of the p-type impurity density in the second region; and a third region located on the rear surface side of the second region and having a p-type impurity density lower than the p-type impurity density in the second region, and a thickness of the second region is thicker than a thickness of the first region.

2 . The diode of claim 1 , wherein the thickness of the second region thicker than a thickness of the third region.

3 . The diode of claim 1 , wherein a width of the first region is narrower than a width of the second region.

4 . A method for manufacturing a diode, the method comprising:
implanting p-type impurities with a first density to a plurality of ranges in a front surface of an n-type semiconductor substrate so that the p-type impurities stop at a first depth, wherein the ranges are arranged at intervals in the front surface; implanting the p-type impurities with a second density to the plurality of ranges so that the p-type impurities stop in a depth range deeper than the first depth, the second density being lower than the first density, wherein the implanting for the p-type impurities with the second density includes a plurality of implantations in which the p-type impurities stop at a plurality of depths in the depth range; forming an anode electrode so as to be in contact with the front surface including the plurality of ranges; and forming a cathode electrode on a rear surface of the semiconductor substrate.

5 . The method of claim 4 , further comprising implanting the p-type impurities with a third density to the plurality of ranges so that the p-type impurities stop at a depth deeper than the depth range, the third density being lower than the second density.

Assignees

• Toyota Motor Co Ltd
• Denso Corp

Inventors

• Miyake Hiroki
• Nagaoka Tatsuji
• Miyahara Shinichiro
• Aoi Sachiko

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21 Primary

  of electrically active species · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/126

  Top-view geometrical layouts of the regions or the junctions · CPC title

• H10D62/106

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title