Scalable periphery tunable matching power amplifier

Patent metadata

Field	Value
Publication number	US-11811367-B2
Application number	US-202217731048-A
Country	US
Kind code	B2
Filing date	Apr 27, 2022
Priority date	Mar 12, 2013
Publication date	Nov 7, 2023
Grant date	Nov 7, 2023

Abstract

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

First claim

The invention claimed is:

1. An amplification circuit, comprising:
one or more amplifiers configured to be selectively activated or deactivated,
wherein each amplifier of the one or more amplifiers comprises:
a stack of a plurality of transistors, and
one or more non-bypassing gate capacitors connected to respective one or more transistors of the plurality of transistors;

wherein, in each amplifier:
an input transistor of the plurality of transistors is configured to receive an input signal through a single common input coupling capacitor, the single common input coupling capacitor being common among the one or more amplifiers,
and
the one or more non-bypassing gate capacitors are configured to allow one or more first radio frequency (RF) gate voltages of respective one or more transistors of the plurality of transistors to vary along with one or more second RF voltages at one or more sources of the respective one or more transistors of the plurality of transistors.

2. The amplification circuit of claim 1 , wherein in each amplifier of the one or more amplifiers at least one cascode transistor of the plurality of transistors is configured to receive a cascode gate voltage.

3. The amplification circuit of claim 2 , wherein in each amplifier of the one or more amplifiers, the one or more non-bypassing gate capacitors are connected between one or more gates of the respective one or more transistors and a reference ground with the exception of the input transistor.

4. The amplification circuit of claim 3 , wherein:
the one or more amplifiers comprise two or more amplifiers;
inputs of the two or more amplifiers are coupled together, and
outputs of the two or more amplifiers are coupled together.

5. The amplification circuit of claim 4 , wherein each of the one or more amplifiers comprises a switch connected in series with a gate of the input transistor, the switch being configured to open or close the input signal path to the input transistor, thus selectively activating or deactivating a corresponding amplifier.

6. The amplification circuit of claim 5 wherein the switch is configured to selectively connect the gate of the input transistor to either the input signal or to a fixed voltage, so as to selectively activate or deactivate the one or more amplifiers.

7. The amplification circuit of claim 4 , wherein each of the one or more amplifiers is configured to be enabled or disabled by a bias voltage applied to a gate of the input transistor.

8. The amplification circuit of claim 4 , wherein each of the one or more amplifiers is configured to be enabled or disabled by one or more bias voltages applied to respective one or more gates of one or more transistors other than the input transistor.

9. The amplification circuit of claim 4 , further comprising an output tunable matching network operatively connected to an output of the amplification circuit, wherein the tunable matching network is configured to adjust an output load impedance seen by the output of the amplification circuit.

10. The amplification circuit of claim 9 , wherein the output tunable matching network comprises:
one or more tunable reactive elements connected between the output of the amplification circuit and the output load; and
a tunable matching control circuit configured to tune the one or more tunable reactive elements to adjust the output load impedance seen by the output of the amplification circuit.

11. The amplification circuit of claim 9 , wherein the output tunable matching network comprises:
a first set of one or more tunable reactive elements placed in series between the output of the amplification circuit and the output load impedance; and/or
a second set of one or more tunable reactive elements placed in parallel with the output load impedance, and
a tunable matching control circuitry configured to tune the first set of the one or more tunable reactive elements and/or the second set of the one or more tunable reactive elements, thus adjusting the output load impedance seen by the output of the amplification circuit.

12. The amplification circuit of claim 9 , wherein the output tunable matching network comprises a plurality of tunable matching networks arranged in one or more of a: a) π-configuration, b) t-configuration, and c) cascade configuration.

13. The amplification circuit of claim 11 , wherein the one or more tunable reactive elements comprise one or more of: a) one or more digital tuning capacitors, and b) one or more digital tuning inductors.

14. The amplification circuit of claim 11 , wherein the one or more amplifiers and one or more of: a) the output tunable matching network in entirety or in part, and b) the tunable matching control circuitry in entirety or in part, are monolithically integrated.

15. The amplification circuit of claim 4 , further comprising a harmonic termination network connected to an output of the amplification circuit.

16. The amplification circuit of claim 15 , wherein the harmonic termination network comprises one or more tunable reactive elements.

17. The amplification circuit of claim 16 , wherein the one or more tunable reactive elements are connected in one of a) series between the output of the amplification circuit and an output load or b) in parallel at the output of the amplification circuit, or a combination thereof.

18. A module comprising the amplification circuit of claim 4 .

19. A cell phone comprising the amplification circuit of claim 4 .

20. A communication device comprising the amplification circuit of claim 4 .

Assignees

• Psemi Corp

Inventors

• Nobbe Dan William
• Halchin David
• Dykstra Jeffrey A
• Gaynor Michael P
• Kovac David
• Mekechuk Kelly Michael
• Kaatz Gary Frederick
• Olson Chris

Classifications

• H03F1/56 Primary

  Modifications of input or output impedances, not otherwise provided for · CPC title

• H03F1/0205

  in transistor amplifiers · CPC title

• H03F1/0261

  with control of the polarisation voltage or current, e.g. gliding Class A · CPC title

• H03F1/0277

  Selecting one or more amplifiers from a plurality of amplifiers · CPC title

• H03F1/223

  with MOSFET's · CPC title