Scalable periphery tunable matching power amplifier

Patent metadata

Field	Value
Publication number	US-9294056-B2
Application number	US-201313797779-A
Country	US
Kind code	B2
Filing date	Mar 12, 2013
Priority date	Mar 12, 2013
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

First claim

The invention claimed is:

1. An amplifier, comprising:
a scalable periphery amplifier comprising one or more unit cells connected in parallel with each other and adapted to be selectively activated or deactivated, wherein each unit cell comprises:
i) a stack of a plurality of transistors configured to operate as an amplifier; and
ii) one or more gate capacitors connected to respective one or more transistors of the plurality of transistors;

an output tunable matching network operatively connected to an output of the scalable periphery amplifier, wherein the tunable matching network is configured to adjust an output load impedance seen by the output of the scalable periphery amplifier; and
an amplifier control circuitry configured to selectively activate or deactivate the one or more unit cells, thus varying a total output power from the amplifier,
wherein:
an input transistor of the plurality of transistors in the stack is configured to receive an input signal of the scalable periphery amplifier;
the one or more gate capacitors are connected between one or more gates of the respective one or more transistors of the plurality of transistors in the stack and a reference ground with the exception of the input transistor; and
a gate capacitor of the one or more gate capacitors is configured to allow a gate voltage of a respective transistor of the one or more transistors to vary along with a radio frequency (RF) voltage at a drain of the respective transistor.

2. The amplifier according to claim 1 , wherein the one or more gate capacitors control voltage drop across the one or more transistors of the plurality of transistors of the stack to substantially equalize an output voltage at an output terminal of the stack across the plurality of transistors of the stack.

3. The amplifier according to claim 1 , further comprising an input tunable matching network operatively connected to an input of the scalable periphery amplifier, wherein an impedance of the input tunable matching network is configured to adjust relative to an input impedance of the input of the scalable periphery amplifier.

4. The amplifier according to claim 1 , wherein each unit cell of the one or more unit cells is a biased unit cell, a bias being applied to said biased unit cell.

5. The amplifier according to claim 3 , wherein each unit cell of the one or more unit cells is a biased unit cell, a bias being applied to said biased unit cell.

6. The amplifier according to any one of claim 2 , 3 , 4 or 5 , wherein the output tunable matching network is configured to be adjusted to switch an operation of the scalable periphery amplifier between two or more classes of amplifier operation.

7. The amplifier according to claim 6 , wherein the output tunable matching network is configured to affect a harmonic termination of the amplifier according to a desired class of amplifier operation.

8. The amplifier according to any one of claim 2 , 3 , 4 or 5 , wherein the amplifier control circuitry is configured to switch an operation of one or more of the unit cells between two or more classes of amplifier operation.

9. The amplifier according to any one of claim 2 , 3 , 4 or 5 , wherein the amplifier control circuitry is configured to select a first class of amplifier operation in correspondence to a first group of unit cells and a second class of amplifier operation in correspondence to a second group of unit cells, wherein the first group of unit cells and the second group of unit cells comprise one or more unit cells from the one or more unit cells.

10. The amplifier according to any one of claim 2 , 3 , 4 or 5 , wherein one or more of: a) the amplifier control circuitry, and b) the output tunable matching network, are configured to affect a desired operating characteristic of the amplifier, the desired operating characteristic of the amplifier comprising one or more of: a) an adjacent channel leakage ratio in correspondence of an output signal power level, b) a power added efficiency (PAE) in correspondence of the output signal power level, c) an output power level, d) a drain current at an output of the amplifier, e) an out of band emission in correspondence of the output signal power level, f) an R X band noise, in correspondence of the output signal power level, and g) an error vector magnitude in correspondence of the output signal power level.

11. The amplifier according to claim 3 or claim 5 , wherein one or more of: a) the amplifier control circuitry, b) the input tunable matching network, and c) the output tunable matching network, are configured to affect a desired operating characteristic of the amplifier, the desired operating characteristic of the amplifier comprising one or more of: a) an adjacent channel leakage ratio in correspondence of an output signal power level, b) a power added efficiency (PAE) in correspondence of the output signal power level, c) an output power level, d) a drain current at an output of the amplifier, e) an out of band emission in correspondence of the output signal power level, f) an R X band noise, in correspondence of the output signal power level, and g) an error vector magnitude in correspondence of the output signal power level.

12. The amplifier according to claim 4 or claim 5 , wherein one or more of: a) the amplifier control circuitry, b) the output tunable matching network, and c) the bias applied to the one or more unit cells, are configured to affect a desired operating characteristic of the amplifier, the desired operating characteristic of the amplifier comprising one or more of: a) an adjacent channel leakage ratio in correspondence of an output signal power level, b) a power added efficiency (PAE) in correspondence of the output signal power level, c) an output power level, d) a drain current at an output of the amplifier, e) an out of band emission in correspondence of the output signal power level, f) an R X band noise, in correspondence of the output signal power level, and g) an error vector magnitude in correspondence of the output signal power level.

13. The amplifier according to claim 5 , wherein one or more of: a) the amplifier control circuitry, b) the input tunable matching network, c) the bias applied to the one or more unit cells, and d) the output tunable matching network, are configured to affect a desired operating characteristic of the amplifier, the desired operating characteristic of the amplifier comprising one or more of: a) an adjacent channel leakage ratio in correspondence to an output signal power level, b) a power added efficiency (PAE) in correspondence of the output signal power level, c) an output power level, d) a drain current at an output of the amplifier, e) an out of band emission in correspondence of the output signal power level, f) an R X band noise, in correspondence of the output signal power level, and g) an error vector magnitude in correspondence of the output signal power level.

14. The amplifier according to claim 10 , further configured to maintain the desired operating characteristic of the amplifier over a range of varying parameters, the varying parameters comprising one or more of: a) a battery voltage providing main power to the amplifier, b) a temperature of the amplifier, c) manufacturing tolerances of the amplifier, d) a band of operation of the amplifier, e) a frequency of operation of the amplifier, f) a peak-to-average ratio of the input signal to the amplifier, g) a modulation scheme of the input signal to the amplifier, h) a bandwidth of the input signal to the amplifier, and i) an input power level of the amplifier.

15. The amplifier accor

Assignees

• Peregrine Semiconductor Corp

Inventors

• Nobbe Dan William
• Halchin David
• Dykstra Jeffrey A
• Gaynor Michael P
• Kovac David
• Mekechuk Kelly Michael
• Kaatz Gary Frederick
• Olson Chris

Classifications

• H03F3/211 Primary

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

• H03F2200/432

  Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier · CPC title

• H03F2200/222

  A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier · CPC title

• H03F1/0277

  Selecting one or more amplifiers from a plurality of amplifiers · CPC title

• H03F1/223

  with MOSFET's · CPC title