Scalable periphery for digital power control

Patent metadata

Field	Value
Publication number	US-9455670-B2
Application number	US-201313948756-A
Country	US
Kind code	B2
Filing date	Jul 23, 2013
Priority date	Jul 23, 2013
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

A scalable periphery digital power control arrangement is presented. The scalable periphery digital power control arrangement comprises a plurality of PMOS transistors connected in parallel, where the plurality of transistors is operatively coupled to a voltage source. The plurality of PMOS transistors that is operatively coupled to the voltage source can operate as a controlled current source. Current flow from the voltage source can be controlled by a logic circuit, which sends a logic signal to enable or disable each individual PMOS transistor of the plurality of PMOS transistors connected in parallel. As more PMOS transistors are enabled, the current flow through the scalable periphery digital power control arrangement to the amplifier can increase.

First claim

The invention claimed is:

1. An arrangement comprising:
an amplifier; and
a power control circuit operatively coupled to the amplifier and adapted to be coupled to a power source, the power control circuit comprising:
a plurality of transistors connected in parallel with one another, the plurality of transistors electrically connected between the power source and an output bias voltage node coupled to the amplifier; and
a logic circuit electrically connected to each of the plurality of transistors, the logic circuit configured, during operation of the arrangement, to send a different logic signal to each transistor of the plurality of transistors to individually enable or disable each transistor of the plurality of transistors;

wherein during operation of the arrangement, a voltage drop through an equivalent parallel resistance of the plurality of transistors of the power control circuit varies as a number of enabled transistors varies, such as to vary an output bias voltage at the output bias voltage node coupled to the amplifier to set a desired output power of the amplifier.

2. The arrangement according to claim 1 , wherein:
each logic signal is a logic high signal or a logic low signal,
the logic circuit sends one of the logic high signal and the logic low signal to enable each transistor of the plurality of transistors, and
the logic circuit sends the other of the logic high signal and the logic low signal to disable each transistor of the plurality of transistors.

3. The arrangement according to claim 1 , wherein an enabled transistor of the plurality of transistors operates in a triode region of operation of the transistor defined by a corresponding equivalent resistance.

4. The arrangement according to claim 1 wherein the voltage drop through the equivalent parallel resistance of the plurality of transistors of the power control circuit, measured between the power source and the amplifier, decreases as the number of enabled transistors increases and increases as the number of enabled transistors decreases, respectively increasing and decreasing the output bias voltage provided to the amplifier.

5. The arrangement according to claim 1 , wherein the plurality of transistors is one of: a) a plurality of PMOS transistors, h) a plurality of stacked PMOS transistors, and c) a plurality of stacked transistors.

6. A device comprising the arrangement according to claim 1 , wherein the device comprises one or more of: a) a GSM amplifier, and b) an amplification path of a constant envelope modulation signal.

7. The arrangement according to claim 5 , wherein the amplifier comprises a transistor.

8. The arrangement according to claim 7 , wherein the transistor is an NMOS transistor.

9. The arrangement according to claim 5 , wherein the amplifier comprises a stack of transistors.

10. The arrangement according to claim 5 , wherein the amplifier is a final stage power amplifier.

11. The arrangement according to claim 1 , further comprising an inductor operatively connected between the power control circuit and the amplifier.

12. The arrangement according to claim 5 , wherein the gate of each of the plurality of transistors connected in parallel receives one of the different logic signals sent by the logic circuit.

13. The arrangement according to claim 5 , wherein the drain of each transistor of the plurality of transistors connected in parallel is connected to a common drain node, where the common drain node is the output bias voltage node at which the output bias voltage is provided.

14. A method of output power control comprising:
providing an amplifier;
providing a power control circuit comprising:
a plurality of transistors connected in parallel, the plurality of transistors adapted to be operatively connected between a power source and an output bias voltage node coupled to the amplifier; and
a logic circuit electrically connected to each transistor of the plurality of transistors;

generating logic signals from the logic circuit, where a number of logic signals corresponds to a number of the transistors connected in parallel;
sending a different logic signal to each transistor of the plurality of transistors to individually enable or disable the particular transistor within the plurality of transistors, and
based on the sending, setting an output power level of the amplifier;
wherein setting the output power level further comprises controlling a voltage drop across an equivalent parallel resistance of the plurality of transistors connected in parallel, wherein the equivalent parallel resistance of the plurality of transistors connected in parallel is dependent on a number of enabled transistors of the plurality of transistors connected in parallel, such as to vary an output bias voltage at the output bias voltage node couple to the amplifier.

15. The method of output power control according to claim 14 , wherein sending the different logic signal comprises:
sending one of a logic high signal and a logic low signal to individually enable a number of transistors of the plurality of transistors, and
sending the other of the logic high signal and the logic low signal to individually disable a remaining number of the plurality of transistors.

16. The method of claim 14 , further comprising providing a desired output power level in correspondence of an output signal of the amplifier and generating of the logic signals based on the providing of the desired output power level.

17. The method of claim 16 , further comprising detecting an output power level of the output signal; based on the detecting, comparing the detected output power level to the desired output power level, and generating the logic signals based on the comparing.

18. The method of claim 16 , further comprising mapping an output power level in correspondence of the output signal to the logic signals and generating the logic signals for a desired output power level based on the mapping.

19. The method of claim 18 , wherein the mapping is stored as digital data in a mapping table.

20. The method of claim 19 , wherein the mapping table further comprises calibration data to compensate for various parameters influencing accuracy of the output power level.

21. The method of claim 20 , wherein the various parameters comprise manufacturing variation of a component used in the amplifier and/or a transistor of the plurality of transistors.

Assignees

• Peregrine Semiconductor Corp

Inventors

• Kovac David

Classifications

• H03F3/72

  Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal · CPC title

• H03F1/223

  with MOSFET's · CPC title

• H03F3/193

  with field-effect devices (H03F3/195 takes precedence) · CPC title

• H03F3/211

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

• H03F2200/15

  the supply or bias voltage or current at the drain side of a FET being continuously controlled by a controlling signal · CPC title