Scalable periphery tunable matching power amplifier

Patent metadata

Field	Value
Publication number	US-9847759-B2
Application number	US-201514957399-A
Country	US
Kind code	B2
Filing date	Dec 2, 2015
Priority date	Mar 12, 2013
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

First claim

The invention claimed is:

1. An amplifier, comprising:
one or more unit cells connected in parallel with each other and adapted to be selectively activated or deactivated, wherein each unit cell comprises:
a) a stack of a plurality of transistors configured to operate as an amplifier; and
b) one or more gate capacitors connected to respective one or more transistors of the plurality of the transistors;

an amplifier control circuitry configured to selectively activate or deactivate the one or more unit cells; wherein:
an input transistor of the plurality of transistors in the stack is configured to receive an input signal;
the one or more gate capacitors are connected between one or more gates of the respective one or more transistors of the plurality of transistors in the stack and a reference ground with the exception of the input transistor, and
a non-bypassing gate capacitor of the one or more gate capacitors is configured to allow a gate voltage of a respective transistor of the plurality of transistors to vary along with a radio frequency (RF) voltage at a drain of the respective transistor.

2. The amplifier of claim 1 , wherein each of the one or more unit cells comprises a switch connected in series with the gate of the input transistor of the stack, the switch being configured to open or close the input signal path to the input transistor, thus selectively activating or deactivating a corresponding unit cell.

3. The amplifier of claim 1 , wherein a bias applied to a transistor of a stack other than the input transistor is configured to be adjusted in correspondence of activating or deactivating a corresponding unit cell.

4. The amplifier of claim 2 , wherein the switch is configured to selectively connect the gate of the input transistor to either the input signal or to a fixed voltage, so as to selectively activate or deactivate the one or more unit cells.

5. The amplifier of claim 1 , wherein each of the one or more unit cells comprises a switch connected in series with a gate of any transistor other than an input transistor of the stack, the switch being configured to turn ON and OFF the transistor thus selectively activating or deactivating the one or more unit cells.

6. The amplifier of claim 1 , wherein each of the one or more unit cells comprises a switch connected in series with a gate of any transistor other than an input transistor of the stack, the switch being configured to selectively connect the transistor to either a first bias voltage or a second bias voltage.

7. The amplifier of claim 6 , wherein each switch is controlled by the amplifier control circuitry.

8. The amplifier of claim 1 , wherein each unit cell of the one or more unit cells is a biased unit cell, a bias being applied to said biased unit cell.

9. The amplifier of claim 2 , wherein each unit cell of the one or more unit cells is a biased unit cell, a bias being applied to said biased unit cell.

10. The amplifier of claim 1 , further comprising an output tunable matching network operatively connected to an output of the amplifier, wherein the tunable matching network is configured to adjust an output load impedance seen by the output of the amplifier.

11. The amplifier of claim 2 , further comprising an output tunable matching network operatively connected to an output of the amplifier, wherein the tunable matching network is configured to adjust an output load impedance seen by the output of the amplifier.

12. The amplifier of claim 10 , further comprising an input tunable matching network operatively connected to an input of the amplifier, wherein an impedance of the input tunable matching network is configured to adjust relative to an input impedance of the input of the amplifier.

13. The amplifier of claim 1 , further comprising a current mirror operatively connected to the gates of the plurality of transistors of the stack, wherein the current mirror is adapted to provide biasing to the plurality of transistors.

14. The amplifier of claim 13 , wherein the current mirror is configured to selectively activate or deactivate a unit cell in correspondence of the plurality of transistors.

15. The amplifier of claim 1 , wherein the input transistor of the plurality of transistors in the stack of each of the one or more unit cells is further configured to receive a bias voltage, the bias voltage being selectively switchable between a first DC voltage and a second DC voltage and wherein during operation, the input signal is received by the input transistor in the stack of each of the one or more unit cells.

16. The amplifier of claim 15 , wherein the second DC voltage is ground.

17. The amplifier of claim 11 , further comprising an input tunable matching network operatively connected to an input of the amplifier, wherein an impedance of the input tunable matching network is configured to adjust relative to an input impedance of the input of the amplifier.

Assignees

• Peregrine Semiconductor Corp

Inventors

• Nobbe Dan William
• Halchin David
• Dykstra Jeffrey A
• Gaynor Michael P
• Kovac David
• Mekechuk Kelly Michael
• Kaatz Gary Frederick
• Olson Chris

Classifications

• H03F3/2176

  Class E amplifiers · CPC title

• H03F2200/108

  A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes · CPC title

• H03F2200/387

  A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier · CPC title

• H03F2200/222

  A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title