Data bus, data processing method thereof, and data processing apparatus

Patent metadata

Field	Value
Publication number	US-11809339-B2
Application number	US-202117191255-A
Country	US
Kind code	B2
Filing date	Mar 3, 2021
Priority date	Mar 6, 2020
Publication date	Nov 7, 2023
Grant date	Nov 7, 2023

Abstract

A data bus includes: a transaction selection circuit configured to receive vector data including a plurality of transactions from outside of the data bus, select at least one transaction from the plurality of transactions in which no traffic conflict occurs based on whether there is a traffic conflict among the plurality of transactions, and output the selected at least one transaction; and a memory data path including at least one register and configured to output the selected at least one transaction provided by the transaction selection circuit via the at least one register to the outside of the data bus.

First claim

What is claimed is:

1. A data bus comprising:
a transaction selection circuit configured to receive vector data including a plurality of transactions from outside of the data bus, select at least one transaction from the plurality of transactions in which no traffic conflict occurs based on whether there is a traffic conflict among the plurality of transactions with reference to a conflict table, and output the selected at least one transaction; and
a memory data path comprising at least one register and configured to output the selected at least one transaction provided by the transaction selection circuit via the at least one register to the outside of the data bus,
wherein the transaction selection circuit selects a row of the conflict table associated with a first transaction of the transactions, references element values of columns of the selected row to determine at least one second transaction of the transactions that has no conflict with the first transaction and sets the at least one transaction to at least one of the first transaction and the at least one second transaction and performs a logical OR operation on at least one column in the conflict table by using all element values included in the corresponding column.

2. The data bus of claim 1 , wherein the transaction selection circuit generates the conflict table including information about whether there is a traffic conflict among the plurality of transactions.

3. The data bus of claim 2 , wherein the transaction selection circuit, after outputting the at least one transaction, updates the conflict table based on information about the at least one transaction, and by selecting at least one other transaction from the plurality of transactions excluding the at least one transaction based on the conflict table, outputs the selected at least one transaction.

4. The data bus of claim 1 , wherein the transaction selection circuit comprises:
a conflict table management circuit configured to generate the conflict table including information about whether there is a traffic conflict among the plurality of transactions, update the conflict table, and output selected information including information about the selected at least one transaction based on the conflict table; and
a transaction output circuit configured to output the selected at least one transaction among the plurality of transactions based on the selected information provided by the conflict table management circuit.

5. The data bus of claim 1 , wherein the transaction selection circuit outputs the selected at least one transaction based on the conflict table,
wherein the conflict table includes a square matrix in which a row length and a column length thereof correspond to a number transactions, and an element value corresponding to an i th row and a j th column includes a value indicating whether there is a traffic conflict between the i th transaction and the j th transaction, and
wherein i and j are natural numbers >=1 and <=the number of transactions.

6. The data bus of claim 1 , wherein the plurality of transactions comprise a first transaction through an N th transaction, and
wherein the transaction selection circuit outputs the selected at least one transaction based on the conflict table,
wherein the conflict table includes a first row through an N th row, all element values of the first row are padded with first logical values, an (i+1) th row includes values indicating whether there is a traffic conflict between an i th transaction and an (i+1) th transaction through the N th transaction, and the N th row includes a value indicating whether there is a traffic conflict between the (N−1) th transaction and the N th transaction,
wherein N is a natural number,
wherein i is a natural number >=1 and (N−2) or less.

7. The data bus of claim 6 , wherein a value indicating whether there is a traffic conflict between an n th transaction and an m th transaction included in the conflict table has a second logical value,
when a sub-bank storing the n th transaction is identical to a sub-bank storing the m th transaction, and a strobe storing the n th transaction is identical to a strobe storing the m th transaction, or when the sub-bank storing the n th transaction is identical to the sub-bank storing the m th transaction, and the strobe storing the n th transaction is different from the strobe storing the m th transaction, a bank storing the n th transaction is identical to a bank storing the m th transaction, and a row storing the n th transaction is different from a row storing the m th transaction,
wherein n and m are natural numbers.

8. The data bus of claim 6 , wherein the transaction selection circuit selects at least one transaction corresponding to a column in which element values of all rows in the conflict table indicate the first logical value and a transaction corresponding to a current row as the selected at least one transaction, and outputs the selected at least one transaction.

9. The data bus of claim 8 , wherein the transaction selection circuit selects at least one transaction corresponding to a column in which a result value of performing the logical OR operation indicates the first logical value as a portion of the selected at least one transaction.

10. The data bus of claim 8 , wherein the transaction selection circuit updates all element values of a row corresponding to the selected at least one transaction in the conflict table to the first logical value, and in response to that at least one element value in the updated conflict table having the second logical value, changes the current row to a row corresponding to one transaction among the plurality of transactions that is unselected.

11. The data bus of claim 1 , wherein the memory data path comprises a plurality of stages, the stages comprising a plurality of registers connected to each other in a tree structure, and the memory data path outputs the selected at least one transaction via the registers corresponding to a last stage among the plurality of stages and via a plurality of output terminals.

12. A data processing method of a data bus, the method comprising:
receiving, by the data bus, vector data including a plurality of transactions;
obtaining, by the data bus, a conflict table including information about whether there is a traffic conflict among the plurality of transactions;
selecting, by the data bus, at least one transaction from the transactions in which no traffic conflict occurs among the plurality of transactions based on the conflict table; and
outputting, by the data bus, the selected at least one transaction,
wherein the selecting comprises:
selecting a row of the conflict table associated with a first transaction of the transactions;
referencing element values of columns of the selected row to determine at least one second transaction of the transactions that has no conflict with the first transaction; and
setting the at least one transaction to at least one of the first transaction and the at least one second transaction,

wherein the plurality of transactions comprise a first transaction through an N th transaction,
wherein the conflict table includes a first row through an N th row, all element values of the first row are padded with first logical values, an (i+1) th row comprises values indicating whether there is a traffic conflict between an i th transaction and an (i+1) th transaction through the N th transaction, and the N th row comprises a value indicating whether there is a traffic conflict between the (N−1) th transaction and the N th transaction,
wherein N is a natural number, and
wherein i is a

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Keongho
• Kim Youngseh
• Kim Wonjin
• Lee Seungbeom

Classifications

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G06F9/3838

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/3824

  Operand accessing · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title