DMA control device, micro control unit, and DMA control method

Patent metadata

Field	Value
Publication number	US-10031871-B2
Application number	US-201514959572-A
Country	US
Kind code	B2
Filing date	Dec 4, 2015
Priority date	Jan 20, 2015
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

A direct memory access (DMA) control device including: a basic-function setting register used to perform DMA operation; and a scatter-gather setting register in which a value indicating that a task is executed through setting of a directly defined value for data to be written to the basic-function setting register without reading the data from a memory through a bus is set.

First claim

What is claimed is:

1. A direct memory access (DMA) control device comprising:
a basic-function setting register used to perform DMA operation; and
a scatter-gather setting register including a first register in which a value indicating one of a plurality of operation modes is set for each of a series of DMA tasks to change details of processing for the each task.

2. The DMA control device according to claim 1 ,
wherein the basic-function setting register includes a configuration register in which a number of pieces of data to be transferred is specified; and
the DMA control device further comprising a configuration-value selection circuit that selects, as a value to be written to the configuration register, either a value read out from a memory coupled to the DMA control device through a bus or a pre-defined value generated in the DMA control device, based on the value in the first register.

3. The DMA control device according to claim 1 ,
wherein the basic-function setting register includes a source-address register in which a source address in a memory is set and a destination-address register in which a copy-destination address in the memory is set; and
the plurality of operation modes includes a mode in which a value in the source address register is used as an immediate value to be written to the copy-destination address in the memory.

4. The DMA control device according to claim 1 ,
wherein the scatter-gather setting register further includes a second register which specifies an address in a memory at which values to be set into the basic-function setting register for the series of DMA tasks are stored.

5. The DMA control device according to claim 4 ,
wherein the scatter-gather setting register further includes a third register which specifies how many DMA tasks are included in the series of DMA tasks.

6. The DMA control device according to claim 5 , further comprising:
a number-of-tasks determination circuit that receives a value in the third register and that determines how many tasks were executed during the scatter-gather operations.

7. The DMA control device according to claim 5 ,
wherein the scatter-gather setting register further includes a fourth register which specifies how many times the series of DMA tasks is repeatedly performed.

8. The DMA control device according to claim 1 , further comprising:
a number-of-repetition determination circuit that determines how many times the series of DMA tasks were repeatedly performed during the scatter-gather operations.

9. A micro control unit comprising:
the DMA control device according to claim 1 ;
a memory;
a central processing unit (CPU);
peripheral circuits; and
a bus that couples the DMA control device, the memory, the CPU, and the peripheral circuits.

10. A direct memory access (DMA) control method having a scatter-gather mode, the method comprising:
writing a setting value to a basic-function setting register for DMA operation,
wherein the scatter-gather mode includes a plurality of different modes, and each task of a series of DMA tasks is executed in a mode specified by a scatter-gather setting register in which one of the plurality of modes is specified for each task of the series of DMA tasks.

11. The DMA control method according to claim 10 ,
wherein, in a first mode among the plurality of different modes, a configuration register, which is included in the basic-function setting register and specifies how many pieces of data are to be transferred, is set to a pre-defined value without being read from a memory through a bus.

12. The DMA control method according to claim 10 ,
wherein, in a second mode among the plurality of different modes, a value in a source-address register included in the basic-function register is used as an immediate value to be written in a destination address of a memory indicated by a destination-address register included in the basic-function setting register.

13. The DMA control method according to claim 10 ,
wherein, in a third mode among the plurality of different modes, a configuration register, which is included in the basic-function setting register and specifies how many pieces of data are to be transferred is set to a pre-defined value without being read from a memory through a bus, and a value in a source-address register included in the basic-function register is used as an immediate value to be written to a destination address indicated by a destination-address register included in the basic-function setting register.

14. The DMA control method according to claim 10 , further comprising:
specifying how many tasks in the series of DMA tasks were executed.

15. The DMA control method according to claim 14 , further comprising:
determining how many times the series of tasks was repeatedly performed.

Assignees

• Fujitsu Ltd

Inventors

• Kawakami Kentaro

Classifications

• G06F13/4063

  Device-to-bus coupling · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• Y02D10/151

  Cross-Sectional Technologies · mapped topic

• Y02D10/14

  Cross-Sectional Technologies · mapped topic