Scatter/gather capable system coherent cache

Patent metadata

Field	Value
Publication number	US-9928170-B2
Application number	US-201615264045-A
Country	US
Kind code	B2
Filing date	Sep 13, 2016
Priority date	May 31, 2013
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

In accordance with some embodiments, a scatter/gather memory approach may be enabled that is exposed or backed by system memory and uses conventional tags and addresses. Thus, such a technique may be more amenable to conventional software developers and their conventional techniques.

First claim

What is claimed is:

1. A method comprising:
using a cache to implement scatter/gather memory access;
backing said cache on system memory;
assigning different multiple addresses within a cache line per clock;
sending a snoop cycle into a tag structure to determine whether a snooping address is in the tag structure, and comparing the snooping address to a tag in said structure to determine whether the snooping address is stored in said tag structure and using said snooping address to access data; and
if multiple cache line lookups address the same cache line in the same clock, serializing the multiple lookups.

2. The method of claim 1 including enabling said cache to use tags.

3. The method of claim 1 including locating said cache between an address generation unit and memory.

4. The method of claim 3 including generating lane enables from the address generation unit.

5. The method of claim 1 including organizing a cache as multiple banks.

6. The method of claim 5 including using tag banking and hashing multiple addresses between banks.

7. The method of claim 1 including multiplexing an output of an address generation unit with an external address from a level 2 cache.

8. One or more non-transitory computer readable media storing instructions executed by a computer to perform a sequence comprising:
using a cache to implement scatter/gather memory access;
backing said cache on system memory;
assigning different multiple addresses within a cache line per clock;
sending a snoop cycle into a tag structure to determine whether a snooping address is in the tag structure, and comparing the snooping address to a tag in said structure to determine whether the snooping address is stored in said tag structure and using said snooping address to access data; and
if multiple cache line lookups address the same cache line in the same clock, serializing the multiple lookups.

9. The media of claim 8 , said sequence including enabling said cache to use tags.

10. The media of claim 8 , said sequence including locating said cache between an address generation unit and memory.

11. The media of claim 10 , said sequence including generating lane enables from the address generation unit.

12. The media of claim 8 , said sequence including organizing a cache as multiple banks.

13. The media of claim 12 , said sequence including using tag banking and hashing multiple addresses between banks.

14. The media of claim 8 , said sequence including multiplexing an output of an address generation unit with an external address from a level 2 cache.

15. An apparatus comprising:
a system memory;
a cache to implement scatter/gather memory access backed on system memory, assign different multiple addressed within a cache line per clock, send a snoop cycle into a tag structure to determine whether a snooping address is in the tag structure, and comparing the snooping address to a tag in said structure to determine whether the snooping address is stored in said tag structure and using said snooping address to access data, if multiple cache line lookups address the same cache line in the same clock, serializing the multiple lookups; and
an address generation unit coupled to said cache.

16. The apparatus of claim 15 said cache to use tags.

17. The apparatus of claim 15 said cache between the address generation unit and system memory.

18. The apparatus of claim 17 from the address generation unit to generate lane enables.

19. The apparatus of claim 15 wherein the cache is organized as multiple banks.

20. The apparatus of claim 19 including said cache to use tag banking and hashing multiple addresses between banks.

21. The apparatus of claim 15 including an operating system.

22. The apparatus of claim 15 including a battery.

23. The apparatus of claim 15 including firmware and a module to update said firmware.

Assignees

• Intel Corp

Inventors

• Koker Altug
• Piazza Thomas A
• Sundaresan Murali

Classifications

• G06F12/128

  adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel · CPC title

• G06F12/0808

  with cache invalidating means (G06F12/0815 takes precedence) · CPC title

• G06F12/0804 Primary

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title