Facilitating efficient prefetching for scatter/gather operations

Patent metadata

Field	Value
Publication number	US-9817762-B2
Application number	US-201414282771-A
Country	US
Kind code	B2
Filing date	May 20, 2014
Priority date	May 20, 2014
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

The disclosed embodiments relate to a computing system that facilitates performing prefetching for scatter/gather operations. During operation, the system receives a scatter/gather prefetch instruction at a processor core, wherein the scatter/gather prefetch instruction specifies a virtual base address, and a plurality of offsets. Next, the system performs a lookup in a translation-lookaside buffer (TLB) using the virtual base address to obtain a physical base address that identifies a physical page for the base address. The system then sends the physical base address and the plurality of offsets to a cache. This enables the cache to perform prefetching operations for the scatter/gather instruction by adding the physical base address to the plurality of offsets to produce a plurality of physical addresses, and then prefetching cache lines for the plurality of physical addresses into the cache.

First claim

What is claimed is:

1. A method for facilitating prefetching for vector-indirect memory operations, comprising:
receiving a vector-indirect prefetch instruction at a processor core, wherein the vector-indirect prefetch instruction specifies a virtual base address, and a plurality of offsets;
performing a single lookup in a translation-lookaside buffer (TLB) using the virtual base address to obtain a physical base address that identifies a physical page for the virtual base address;
sending the physical base address and the plurality of offsets to a cache; and
at the cache, performing prefetching operations for the vector-indirect prefetch instruction by,
adding the physical base address from the single lookup to the plurality of offsets to produce a plurality of physical addresses,
for each physical address in the plurality of physical addresses that fall within the physical page, prefetching cache lines for the plurality of physical addresses into the cache, and
for each physical address in the plurality of physical addresses that fall outside of the physical page, no prefetching operation is performed.

2. The method of claim 1 , wherein producing the plurality of physical addresses includes combining physical addresses when two or more associated offsets fall within a single cache line.

3. The method of claim 1 , wherein if the vector-indirect prefetch instruction is a scatter prefetch instruction, the cache lines are prefetched into the cache in a modifiable state.

4. The method of claim 1 , wherein if a vector/indirect prefetch instruction causes a cache miss, and a buffer associated with the vector-indirect prefetch instruction is full, the vector-indirect prefetch instruction is dropped.

5. The method of claim 1 , wherein if the TLB lookup causes a TLB miss, the method further comprises:
using a hardware table walker to retrieve an associated page table entry for the virtual base address into the TLB; and
replaying the vector-indirect prefetch instruction.

6. The method of claim 1 , wherein the vector-indirect prefetch instruction identifies:
a first register associated with the virtual base address; and
a second register that contains a pointer to a block of memory containing the plurality of offsets.

7. The method of claim 1 , wherein the vector-indirect prefetch instruction identifies:
a first register associated with the virtual base address; and
one or more second registers that contain the plurality of offsets.

8. The method of claim 7 ,
wherein the vector-indirect prefetch instruction is a modification of a block store instruction;
wherein the first register, which is normally used to identify a store target location, is repurposed to identify the virtual base address; and
wherein the one or more second registers, which normally hold a block of data to be stored, are repurposed to hold a block of memory containing the plurality of offsets.

9. The method of claim 1 , wherein the cache is one of:
a Level 2 (L2) cache;
a Level 3 (L3) cache;
a Level 4 (L4) cache; and
another cache in a memory hierarchy accessed by the processor core.

10. A processor that facilitates prefetching for vector-indirect memory operations, comprising:
a processor core;
a cache in communication with the processor core; and
an execution mechanism within the processor core, wherein the execution mechanism is configured to,
receive a vector-indirect prefetch instruction, wherein the vector-indirect prefetch instruction specifies a virtual base address, and a plurality of offsets,
perform a single lookup in a translation-lookaside buffer (TLB) using the virtual base address to obtain a physical base address that identifies a physical page for the virtual base address,
send the physical base address and the plurality of offsets to the cache; and

wherein upon receiving the physical base address and the plurality of offsets, the cache is configured to,
add the physical base address from the single lookup to the plurality of offsets to produce a plurality of physical addresses,
for each physical address in the plurality of physical addresses that fall within the physical page, prefetch cache lines for the plurality of physical addresses into the cache; and
for each physical address in the plurality of physical addresses that fall outside of the physical page, no prefetching operation is performed.

11. The processor of claim 10 , wherein if the vector-indirect prefetch instruction is a scatter prefetch instruction, the cache prefetches the cache lines into the cache in a modifiable state.

12. The processor of claim 10 , wherein if a vector-indirect prefetch instruction causes a cache miss, and a buffer associated with the vector-indirect prefetch instruction is full, the cache drops the vector-indirect prefetch instruction.

13. The processor of claim 10 , wherein if the TLB lookup causes a TLB miss, the execution mechanism is configured to:
use a hardware table walker to retrieve an associated page table entry for the virtual base address into the TLB; and
replay the vector-indirect prefetch instruction.

14. The processor of claim 10 , wherein the vector-indirect prefetch instruction identifies:
a first register associated with the virtual base address; and
one or more second registers that contain the plurality of offsets.

15. The processor of claim 14 ,
wherein the vector-indirect prefetch instruction is a modification of a block store instruction;
wherein the first register, which is normally used to identify a store target location, is repurposed to identify the virtual base address; and
wherein the one or more second registers, which normally hold a block of data to be stored, are repurposed to hold a block of memory containing the plurality of offsets.

16. A computer system that facilitates prefetching for vector-indirect memory operations, comprising:
a processor;
a cache associated with the processor;
a memory; and
an execution mechanism within the processor, wherein the execution mechanism is configured to,
receive a vector-indirect prefetch instruction, wherein the vector-indirect prefetch instruction specifies a virtual base address, and a plurality of offsets,
perform a single lookup in a translation-lookaside buffer (TLB) using the virtual base address to obtain a physical base address that identifies a physical page for the virtual base address,
send the physical base address and the plurality of offsets to the cache; and

wherein upon receiving the physical base address and the plurality of offsets, the cache is configured to,
add the physical base address from the single lookup to the plurality of offsets to produce a plurality of physical addresses,
for each physical address in the plurality of physical addresses that fall within the physical page, prefetch cache lines for the plurality of physical addresses into the cache; and
for each physical address in the plurality of physical addresses that fall outside of the physical page, no prefetching operation is performed.

Assignees

• Oracle Int Corp

Inventors

• Kapil Sanjiv
• Gove Darryl J

Classifications

• G06F12/0862 Primary

  with prefetch · CPC title

• G06F2212/681

  Multi-level TLB, e.g. microTLB and main TLB · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/10

  Address translation · CPC title

• G06F2212/6028

  Prefetching based on hints or prefetch instructions · CPC title