Superconductor-based transistor

Patent metadata

Field	Value
Publication number	US-11805709-B2
Application number	US-202016813628-A
Country	US
Kind code	B2
Filing date	Mar 9, 2020
Priority date	Jul 28, 2017
Publication date	Oct 31, 2023
Grant date	Oct 31, 2023

Abstract

The various embodiments described herein include methods, devices, and systems for fabricating and operating transistors. In one aspect, a transistor includes: (1) a semiconducting component configured to operate in an on state at temperatures above a semiconducting threshold temperature; and (2) a superconducting component configured to operate in a superconducting state while: (a) a temperature of the superconducting component is below a superconducting threshold temperature; and (b) a first current supplied to the superconducting component is below a current threshold; where: (i) the semiconducting component is located adjacent to the superconducting component; and (ii) in response to a first input voltage, the semiconducting component is configured to generate an electromagnetic field sufficient to lower the current threshold such that the first current exceeds the lowered current threshold, thereby transitioning the superconducting component to a non-superconducting state.

First claim

What is claimed is:

1. A transistor, comprising:
a superconducting wire on a first layer of the transistor;
a semiconducting wire on a second layer of the transistor, the semiconducting wire configured to transfer current from a source of the transistor to a drain of the transistor; and
an electrically-insulating layer electrically isolating the first layer from the second layer, wherein the transistor is configured to switch from an off state to an on state when the superconducting wire is above a superconducting temperature threshold.

2. The transistor of claim 1 , wherein the superconducting wire comprises a gate of the transistor and the semiconducting wire comprises the source and drain of the transistor.

3. The transistor of claim 1 , wherein a superconducting threshold temperature of the superconducting wire is adjacent to a semiconducting threshold temperature of the semiconducting wire.

4. The transistor of claim 1 , wherein the superconducting wire has a constricted region at a location adjacent to the semiconducting wire.

5. The transistor of claim 1 , wherein the superconducting wire is configured to generate heat at a location adjacent to the semiconducting wire during a transition from a superconducting state to a non-superconducting state of the superconducting wire.

6. The transistor of claim 1 , wherein the semiconducting wire includes Germanium.

7. The transistor of claim 1 , wherein the semiconducting wire has a first region adjacent to the superconducting wire and secondary regions neighboring the first region.

8. The transistor of claim 7 , wherein the first region is configured to operate in an on state at temperatures above a semiconducting threshold temperature and the secondary regions are configured to operate in the on state at temperatures above a second semiconducting threshold temperature, the second semiconducting threshold temperature being below the semiconducting threshold temperature.

9. The transistor of claim 7 , wherein the first region is narrower than the secondary regions.

10. The transistor of claim 1 , wherein the superconducting wire is perpendicular to the semiconducting wire.

11. The transistor of claim 1 , wherein the superconducting wire is parallel to the semiconducting wire.

12. The transistor of claim 1 , wherein the electrically-insulating layer is thermally conductive.

13. The transistor of claim 12 , wherein the electrically-insulating layer is configured to conduct heat generated at the superconducting wire to the semiconducting wire, thereby raising a temperature of the semiconducting wire.

14. The transistor of claim 1 , wherein the transistor is configured to remain in the off state when the superconducting wire is maintained at a temperature that is below a temperature threshold of the superconducting wire.

15. A method for operating a superconductor-based transistor, comprising:
maintaining the superconductor-based transistor in an off state, wherein the superconductor-based transistor includes a first wire including a semiconducting component and a second wire including a superconducting component; and
while the superconducting component of the superconductor-based transistor is operating in a superconducting state, and the semiconducting component of the superconductor-based transistor is in an off state, initiating transition of the superconductor-based transistor from the off state to an on state by supplying a current to the superconducting component, wherein the current exceeds a superconducting current threshold for the superconducting component;
whereby, in response to the current supplied to the superconducting component, the superconducting component transitions to a non-superconducting state and generates heat sufficient to increase a temperature of the semiconducting component above a semiconducting threshold temperature and enable current flow through the semiconducting component.

16. The method of claim 15 , wherein maintaining the superconductor-based transistor in an off state comprises maintaining the superconducting component below a superconducting temperature.

17. The method of claim 15 , wherein maintaining the superconductor-based transistor in an off state comprises supplying a current to the superconducting component that is below the superconducting current threshold.

Assignees

• Psiquantum Corp

Inventors

• Najafi Faraz

Classifications

• H10D64/608 Primary

  being superconducting · CPC title

• H10D30/6733

  Multi-gate TFTs · CPC title

• H10F99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10F77/206

  for devices having potential barriers · CPC title

• H10F30/282

  Insulated-gate field-effect transistors [IGFET], e.g. MISFET [metal-insulator-semiconductor field-effect transistor] phototransistors · CPC title