Low-power biasing networks for superconducting integrated circuits

Patent metadata

Field	Value
Publication number	US-9853645-B1
Application number	US-201615290583-A
Country	US
Kind code	B1
Filing date	Oct 11, 2016
Priority date	Oct 12, 2009
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A superconducting integrated circuit, comprising a plurality of superconducting circuit elements, each having a variation in operating voltage over time; a common power line; and a plurality of bias circuits, each connected to the common power line, and to a respective superconducting circuit element, wherein each respective bias circuit is superconducting during at least one time portion of the operation of a respective superconducting circuit element, and is configured to supply the variation in operating voltage over time to the respective superconducting circuit element.

First claim

What is claimed is:

1. A biasing network for a biasing circuit elements in a plurality of parallel circuit branches, comprising:
a current distribution network;
a bias element for each respective parallel circuit branch, comprising at least one Josephson junction having a critical current I C connected in series with at least one inductor, effective for biasing the respective circuit branch with a bias current I n and for critically damping at least one Josephson junction within the respective circuit branch;
each bias element communicating a respective bias current I n from the current distribution network to respective circuit elements in each respective circuit branch,
each bias element having a respective inductance L n such that the respective bias current I n of each respective circuit branch is inversely proportional to L n , where L n I n is greater than Φ 0 =h/2e=2 mA-pH.

2. The biasing network according to claim 1 , wherein at least one first circuit element in a first respective circuit branch has a different respective operating voltage than at least one second circuit element in a second respective circuit branch.

3. The biasing network according to claim 1 , wherein at least one first circuit element in a first respective circuit branch has a different respective bias current I C than at least one second circuit element in a second respective circuit branch.

4. The biasing network according to claim 1 , wherein at least one first circuit element in a first respective circuit branch comprises of a Josephson junction connected to a ground.

5. The biasing network according to claim 1 , wherein at least one first circuit element in a first respective circuit branch comprises of a Josephson transmission line (JTL).

6. The biasing network according to claim 1 , wherein at least one first circuit element in a first respective circuit branch comprises of a superconducting flip flop.

7. The biasing network according to claim 1 , wherein at least one first circuit element in a first respective circuit branch comprises of a superconducting toggle flip-flop (TFF).

8. The biasing network according to claim 1 , wherein at least one first circuit element in a first respective circuit branch comprises of a single flux quantum logic element.

9. The biasing network according to claim 1 , wherein the at least one inductor for each respective circuit branch is a superconducting inductor.

10. The biasing network according to claim 1 , wherein the bias element for each respective circuit branch functions as a current limiter.

11. The biasing network according to claim 1 , at least one circuit branch comprises a Josephson junction circuit substantially without any shunt resistor in parallel with a Josephson junction.

12. The biasing network according to claim 1 , wherein a first bias element exhibits a maximum average DC voltage V max , a second bias element that exhibits a maximum average DC voltage V n <V max , wherein a respective ratio of an average bias current Ī C for the first bias element and the second bias element is not proportional to a respective ratio of V max to V n .

13. The biasing network according to claim 12 , wherein the second bias element exhibits an average voltage drop of V max −V n .

14. A method of biasing circuit elements in a plurality of parallel circuit branches, comprising:
distributing a current through a current distribution network to the plurality of parallel circuit branches;
providing a respective bias element for each respective circuit branch, each respective bias element comprising at least one Josephson junction having a critical current I C connected in series with at least one inductor, effective for biasing the respective circuit branch with a bias current I n and for critically damping at least one Josephson junction within the respective circuit branch;
communicating the respective bias current I n from the current distribution network, through each respective bias element, to respective circuit elements in each respective circuit branch, such that each respective circuit branch is supplied with a respective bias current I n and at least one Josephson junction within the respective circuit branch is critically damped by the respective bias element substantially without a shunt damping impedance within the respective circuit branch for damping the at least one Josephson junction within that respective branch.

15. The method according to claim 14 , wherein each bias element has a respective inductance L n such that the respective bias current I n of each respective circuit branch is inversely proportional to L n , where L n I n is greater than Φ 0 =h/2e=2 mA-pH.

16. The method according to claim 15 , wherein a plurality of respective circuit branches comprise single flux quantum logic circuits, further comprising communicating an output of the single flux quantum logic circuits.

17. The method according to claim 14 , wherein at least one first circuit element in a first respective circuit branch has a different respective average operating voltage and average operating current than at least one second circuit element in a second respective circuit branch, wherein the respective bias element for each respective branch operates as a current limiter.

18. The method according to claim 14 , wherein the at least one inductor for each respective circuit branch is a superconducting inductor.

19. The method according to claim 14 , further comprising turning on and off at least one circuit branch such that it selectively operates when turned on.

20. A superconducting integrated circuit, comprising:
a plurality of superconducting circuit elements, each being biased below a critical current for a respective superconducting Josephson junction logic element within the respective circuit element; and
a biasing network comprising a plurality of bias elements in parallel, configured to dynamically critically bias the plurality of superconducting circuit elements, while substantially isolating a dynamic bias state for each of the plurality of superconducting circuit elements from others of the plurality of superconducting circuit elements, each bias element being configured to receive a bias current from a current source and pass the bias current through at least one inductor and at least one bias Josephson junction, the bias current for each respective bias element being dependent on a critical current of the respective bias Josephson junction,
wherein the plurality of superconducting circuit elements are configured to operate in a stable operating regime over a range of data sequences input to the superconducting integrated circuit and fed to the plurality of superconducting circuit elements.

Assignees

• Hypres Inc

Inventors

• Mukhanov Oleg A
• Kirichenko Alexander F
• Kirichenko Dimitri

Classifications

• H03K19/195 Primary

  using superconductive devices · CPC title

• H03K3/38

  by the use, as active elements, of superconductive devices · CPC title

• Y10T29/49124

  On flat or curved insulated base, e.g., printed circuit, etc. · CPC title

• H01B12/16

  characterised by cooling · CPC title

• H01B12/02

  characterised by their form · CPC title