Josephson magnetic random access memory with an inductive-shunt

Patent metadata

Field	Value
Publication number	US-9443576-B1
Application number	US-201514935862-A
Country	US
Kind code	B1
Filing date	Nov 9, 2015
Priority date	Nov 9, 2015
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A memory system includes a word-line coupled to memory cells in a row, and a bit-line coupled to memory cells in a column. Each of the memory cells includes a memory storage element including a Josephson junction configured to be in either a first state or a second state in response to an application of a word-line current to the Josephson junction. A read operation is performed on the at least one memory storage element by an application of a bit-line current to the bit-line. At least one inductive-shunt, coupled in parallel to the at least one memory storage element, is configured to, after the read operation, remove at least a substantial portion of the bit-line current provided to the at least one memory storage element without requiring removal of an entirety of the bit-line current applied to the bit-line during the read operation.

First claim

What is claimed:

1. A memory system comprising:
an array of memory cells arranged in rows and columns;
a first set of word-lines, wherein each of the first set of the word-lines is coupled to a first plurality of memory cells in at least one row;
a first set of bit-lines, wherein each of the first set of the bit-lines is coupled to a second plurality of memory cells in at least one column;
wherein each of the first plurality of the memory cells and each of the second plurality of the memory cells comprises:
at least one memory storage element comprising at least one Josephson junction configured to be in either a first state or a second state in response to an application of a word-line current, via the at least one of the first set of the word-lines, to the at least one Josephson junction, and wherein a read operation on the at least one memory storage element is performed in response to an application of a bit-line current to the at least one of the first set of the bit-lines; and

at least one inductive-shunt coupled in parallel to the at least one memory storage element, wherein the inductive-shunt is configured to after the read operation, remove at least a substantial portion of the bit-line current provided to the at least one memory storage element without requiring removal of an entirety of the bit-line current applied to the at least one of the first set of the bit-lines during the read operation.

2. The memory system of claim 1 , wherein the at least one inductive-shunt comprises at least one resistor coupled in series with at least one inductor.

3. The memory system of claim 2 , wherein, the resistor in the at least one inductive-shunt is configured to, after completion of the read operation, redirect the bit-line current to the at least one of the first set of the bit-lines before a next read operation.

4. The memory system of claim 1 , wherein the at least one inductive-shunt is configured to remove the substantial portion of the bit-line current provided to the at least one memory storage element without de-coupling the at least one of the first set of the bit-lines from the at least one memory storage element.

5. The memory system of claim 1 , wherein the at least one inductive-shunt is further configured such that the substantial portion of the bit-line current removed by the inductive-shunt is sufficient to turn-off the at least one memory cell.

6. The memory system of claim 1 , wherein the memory system comprises components based on reciprocal quantum logic, and wherein the at least one memory cell further comprises an inductor coupled to the at least one Josephson junction to form a superconducting quantum interference device (SQUID).

7. The memory system of claim 1 , wherein the at least one Josephson junction comprises at least one magnetic barrier layer, and wherein the first state comprises a first magnetization state corresponding to a first configuration of magnetization of the at least one magnetic barrier layer and the second state comprises a second magnetization state corresponding to a second configuration of magnetization of the at least one magnetic barrier layer, wherein the first configuration of the magnetization is substantially different from the second configuration of the magnetization.

8. A method in a memory system comprising an array of memory cells arranged in rows and columns, a first set of word-lines, wherein each of the first set of word-lines is coupled to a first plurality of memory cells in at least one row, a first set of bit-lines, wherein each of the first set of the bit-lines is coupled to a second plurality of memory cells in at least one column, wherein each of the first plurality of the memory cells and each of the plurality of the second plurality of the memory cells comprises at least one memory storage element comprising at least one Josephson junction, the method comprising:
performing a first read operation in response to a first bit-line current applied to at least one of the first set of the bit-lines and a first word-line current applied to at least one of the first set of word-lines; and
using an inductive-shunt, coupled in parallel to the at least one memory storage element, removing at least a substantial portion of the first bit-line current provided to the at least one memory storage element during the first read operation, without requiring removal of an entirety of the first bit-line current applied to the at least one of the first set of the bit-lines during the first read operation.

9. The method of claim 8 , wherein the inductive-shunt comprises at least one resistor coupled in series with at least one inductor.

10. The method of claim 8 , wherein during the first read operation, the at least one memory storage element is in a first state or a second state, and wherein the first state is a voltage state and the second state is a zero-state.

11. The method of claim 8 further comprising removing the at least the substantial portion of the first bit-line current provided to the at least one memory storage element, without de-coupling the at least one memory storage element from the at least one of the first set of bit-lines.

12. The method of claim 8 , wherein the removing the at least the substantial portion of the first bit-line current provided to the at least one memory storage element further comprises removing a sufficient current so as to turn-off the at least one memory cell.

13. The method of claim 12 further comprising, after a predetermined number of clock cycles, performing a second read operation in response to a second bit-line current applied to the at least one of the first set of the bit-lines.

14. The method of claim 13 , wherein the memory system comprises components based on reciprocal quantum logic, and wherein the clock cycles correspond to a sinusoidal clock.

15. A memory system comprising:
an array of memory cells arranged in rows and columns;
a first set of word-lines, wherein each of the first set of word-lines is coupled to a first plurality of memory cells in at least one row;
a first set of bit-lines, wherein each of the first set of bit-lines is coupled to a second plurality of memory cells in at least one column;
wherein each of the first plurality of the memory cells and each of the second plurality of the memory cells comprises:
at least one memory storage element comprising at least one Josephson junction comprising at least one magnetic barrier layer, wherein the at least one magnetic barrier layer is configured to be in either a first magnetization state or a second magnetization state in response to an application of a word-line current, via at least one of the first set of the word-lines, to the at least one Josephson junction,
wherein a read operation on the at least one memory storage element is performed by an application of a bit-line current to the at least one of the first set of the bit-lines; and

at least one inductive-shunt coupled in parallel to at least N memory storage elements, wherein N is a positive integer, and wherein the inductive-shunt is configured to after the read operation, remove at least a substantial portion of the bit-line current provided to the at least the N memory storage elements without requiring removal of an entirety of the bit-line current applied to the at least one of the first set of the bit-lines during the read operation.

16. The memory system of claim 15 , wherein the at least one inductive-shunt comprises a resistor coupled in series with an inductor.

17. The memory system of claim 15 , wherein the at least one inductiv

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Miller Donald L

Classifications

• G11C11/44 Primary

  using super-conductive elements, e.g. cryotron · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title