Superconducting quantum logic and applications of same

Patent metadata

Field	Value
Publication number	US-9998122-B2
Application number	US-201715617727-A
Country	US
Kind code	B2
Filing date	Jun 8, 2017
Priority date	Jun 8, 2016
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A superconducting logic cell includes at least one quantum phase-slip junction (QPSJ) for receiving at least one input and responsively providing at least one output, each QPSJ being configured such that when an input voltage of an input voltage pulse exceeds a critical value, a quantized charge of a Cooper electron pair tunnels across said QPSJ as an output, when the input voltage is less than the critical value, no quantized charge of the Cooper electron pair tunnels across said QPSJ as the output, where the presence and absence of the quantized charge in the form of a constant area current pulse in the output form two logic states, and the at least one QPSJ is biased with a bias voltage. The superconducting logic cell further includes at least one Josephson junction (JJ) coupled with the at least one QPSJ to perform one or more logic operations.

First claim

What is claimed is:

1. A superconducting logic cell, comprising:
at least one quantum phase-slip junction (QPSJ) for receiving at least one input and responsively providing at least one output, each QPSJ being configured such that when an input voltage of an input voltage pulse exceeds a critical value, a quantized charge of a Cooper electron pair tunnels across said QPSJ as an output, when the input voltage is less than the critical value, no quantized charge of the Cooper electron pair tunnels across said QPSJ as the output, wherein the presence and absence of the quantized charge that is realizable as a constant area of current pulses in the output form two logic states, and wherein the at least one QPSJ is biased with a bias voltage,
wherein the bias voltage is about 50-95% of the critical voltage, the input voltage is at least about 110% of the critical voltage for quantized charge tunneling.

2. The superconducting logic cell of claim 1 , wherein each QPSJ is characterizable as a compact circuit model, wherein the compact circuit model comprises a voltage source, a phase-slip junction, an inductor representing an inductance of a nano-wire of the phase-slip junction, and a non-linear resistor having different values of resistance in different phases of operation and showing normal to superconductor transition as a function of the voltage across the phase-slip junction, coupling to each other in series.

3. The superconducting logic cell of claim 2 , wherein the critical voltage, the inductance, and the resistance are determined by material properties and physical dimensions of the QPSJ.

4. The superconducting logic cell of claim 1 , wherein the at least one QPSJ comprises two QPSJs, wherein a node connecting two QPSJs and a capacitor defines a charge island.

5. The superconducting logic cell of claim 4 , wherein when the quantized charge of the Cooper electron pair tunnels across one of the two QPSJs, the quantized charge of the Cooper electron pair is stored in the charge island, otherwise no quantized charge of the Cooper electron pair is stored in the charge island, thereby forming a basic logic element having the two logic states.

6. The superconducting logic cell of claim 1 , being a QPSJ transmission line, wherein the at least one QPSJ comprises a plurality of QPSJs connected to one another in series, wherein each node connecting two adjacent QPSJs and a capacitor defines a charge island.

7. The superconducting logic cell of claim 6 , wherein the quantized charge of the Cooper electron pair is stored in a charge island or forced to hop to its immediately next charge island, by design of or tuning a capacitance of the charge island, along with the junction parameters, thereby transferring the quantized charge of the Cooper electron pair along the QPSJ transmission line.

8. The superconducting logic cell of claim 6 , wherein amplification or attenuation of the current pulse amplitude is obtained by using the QPSJs of different critical voltages and different capacitor values.

9. The superconducting logic cell of claim 1 , being a QPSJ pulse splitter, wherein the at least one QPSJ comprises three QPSJs, wherein
the first QPSJ has a first terminal connected to an input voltage source defining an input node, and a second terminal connected to a first capacitor;
the second QPSJ has a first terminal connected to the second terminal of the first QPSJ, and a second terminal connected to a second capacitor and a first bias voltage source defining a first output node; and
the third QPSJ has a first terminal connected to the second terminal of the first QPSJ, and a second terminal connected to a third capacitor and a second bias voltage source defining a second output node,
wherein in operation, an input pulse at the input node is split into two pulses output from the first and second output nodes respectively.

10. The superconducting logic cell of claim 1 , being a QPSJ buffer, wherein the at least one QPSJ comprises three QPSJs, wherein
the first QPSJ has a first terminal connected to an input voltage source or a first bias voltage source defining a first node, and a second terminal connected to a first capacitor defining a second node;
the second QPSJ has a first terminal connected to the second terminal of the first QPSJ defining a third node, and a second terminal connected to a second capacitor and the first bias voltage source or the input voltage source defining a fourth node; and
the third QPSJ has a first terminal connected to the third node, and a second terminal connected to a second bias voltage source,
wherein in operation, an input pulse from the first node through the first QPSJ switches to the third QPSJ, before it switches to the second QPSJ so as to prevent a signal flow in a direction from the first node to the fourth node, or when current arrives from an opposite direction, the first QPSJ switches before the third QPSJ, allowing the signal through.

11. The superconducting logic cell of claim 1 , being a QPSJ confluence buffer, wherein the at least one QPSJ comprises four QPSJs, wherein
the first QPSJ has a first terminal connected to a first input voltage source, and a second terminal connected to a first capacitor defining node 3 ;
the second QPSJ has a first terminal connected to a second input voltage source, and a second terminal connected to a second capacitor defining node 6 , wherein both nodes 3 and 6 are connected to node 7 ;
the third QPSJ has a first terminal connected to node 7 , and a second terminal connected to a first bias voltage source; and
the fourth QPSJ has a first terminal connected to node 7 , and a second terminal connected to a third capacitor and the second bias voltage source at node 8 ,
wherein in operation, input pulses from either the first or second input voltage sources result in an output pulse from node 8 , but do not result in output from the other input.

12. The superconducting logic cell of claim 11 , being a QPSJ based OR gate, wherein the at least one QPSJ comprises six QPSJs, wherein the first to fourth QPSJs define the confluence buffer and the fifth and sixth QPSJs define an island, wherein the confluence buffer is connected to the island in series such that a first terminal of the fifth QPSJ is connected to the output terminal of the confluence buffer and a second terminal of the sixth QPSJ is connected to a clock signal of a third input voltage source that is connected to a second bias voltage source.

13. The superconducting logic cell of claim 11 , being a QPSJ based AND gate, wherein the at least one QPSJ comprises five QPSJs, wherein the first to fourth QPSJs define the confluence buffer and the fifth QPSJ has a first terminal connected to the output terminal of the confluence buffer and a second terminal connected to a second bias voltage source, and the output terminal of the confluence buffer is connected to a clock signal of a third input voltage source that is connected to a second bias voltage source.

14. The superconducting logic cell of claim 11 , being a QPSJ based XOR gate, wherein the at least one QPSJ comprises four QPSJs, wherein the first to fourth QPSJs define the confluence buffer and the output terminal of the confluence buffer is connected to a clock signal of a third input voltage source that is connected to a second bias voltage source.

15. The superconducting logic cell of claim 1 , being an RS flip-flop or a D flip-flop, wherein the at least one QPSJ comprises two QPSJs, wherein
the first QPSJ has a first terminal connected to a bias voltage source at node 2 that in turn is connected to a first input voltage sourc

Assignees

• Univ Auburn

Inventors

• Hamilton Michael C
• Goteti Uday S

Classifications

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H03K3/38

  by the use, as active elements, of superconductive devices · CPC title

• H03K19/195 Primary

  using superconductive devices · CPC title