Method of fabrication thereof a multi-level vertical memory device including inter-level channel connector

Patent metadata

Field	Value
Publication number	US-11805643-B2
Application number	US-202117462736-A
Country	US
Kind code	B2
Filing date	Aug 31, 2021
Priority date	Sep 27, 2018
Publication date	Oct 31, 2023
Grant date	Oct 31, 2023

Abstract

Aspects of the disclosure provide methods for manufacturing semiconductor devices. One of the methods forms a string of transistors in a semiconductor device over a substrate of the semiconductor device. The method includes forming a first substring of transistors having a first channel structure that includes a first channel layer and a first gate dielectric structure that extend along a vertical direction over the substrate. The method includes forming a channel connector over the first substring and forming the second substring above the channel connector. The second substring has a second channel structure. The second channel structure includes the second channel layer and a second gate dielectric structure that extend along the vertical direction. The second gate dielectric structure is formed above the channel connector. The channel connector electrically couples the first channel layer and the second channel layer.

First claim

What is claimed is:

1. A method for manufacturing a string of transistors in a semiconductor device over a substrate of the semiconductor device, comprising:
forming a first substring of transistors having a first channel structure that includes a first channel layer and a first gate dielectric structure that extend along a vertical direction over the substrate;
forming a channel connector over the first substring that includes a first structure having a first recessed region and a second structure that is formed by overfilling the first recessed region, the second structure including a second recessed region; and
forming a second substring of transistors above the channel connector, the second substring having a second channel structure that includes a second channel layer and a second gate dielectric structure that extend along the vertical direction, the second gate dielectric structure being formed above the channel connector, the channel connector electrically coupling the first channel layer and the second channel layer, wherein
the second channel layer extends into the second recessed region and contacts sidewalls of the second recessed region and an upper surface of the second recessed region is fully covered by a contact that is connected to the second channel layer, the contact electrically coupling the second channel layer and the second structure.

2. The method according to claim 1 , wherein the forming the second substring above the channel connector comprises forming the second gate dielectric structure adjacent to and above the second structure, the second gate dielectric structure being separated from the first structure by the second structure.

3. The method according to claim 2 , wherein the forming the first structure comprises:
forming an opening in an insulating layer over the first substring, a bottom portion of the opening exposing the first channel structure; and
depositing a semiconductor material over the first channel structure.

4. The method according to claim 1 , wherein the forming the second structure comprises:
forming the second structure by epitaxially growing a semiconductor material over an upper surface of the first recessed region in the first structure.

5. The method according to claim 4 , further comprising:
forming the first structure in contact with the first channel layer; and
forming the second channel layer in contact with and disposed above the second structure.

6. The method according to claim 1 , wherein the forming the channel connector further comprises:
forming the first structure in contact with the first channel layer and having an upper surface of the first recessed region; and
forming the second structure in the first recessed region, the second structure having the upper surface of the second recessed region, the upper surface of the second recessed region being above the upper surface of the first recessed region, and
the second gate dielectric structure being above the upper surface of the second recessed region.

7. The method according to claim 1 , further comprising:
forming a recess in an upper surface of the channel connector;
forming the second gate dielectric structure on the upper surface of the channel connector; and
forming the second channel layer in the recess.

8. The method according to claim 1 , further comprising:
forming the second gate dielectric structure on an upper surface of the channel connector; and
forming the second channel layer over the second gate dielectric structure and over the second recessed region.

9. The method according to claim 1 , further comprising:
forming a plurality of first gate structures stacked along the vertical direction and separated by insulating layers, the first gate structures being separated from the first channel layer by the first gate dielectric structure; and
forming a plurality of second gate structures stacked along the vertical direction and separated by other insulating layers, the second gate structures are separated from the second channel layer by the second gate dielectric structure, the first and second gate structures being configured to control operations of the respective transistors in the first and second substrings.

10. The method according to claim 1 , wherein the channel connector includes the first structure and the second structure that is above the first structure, a top surface of the second structure is below a bottom surface of a bottom one of the second gate structures.

11. The method according to claim 1 , wherein the channel connector includes one or more semiconductor materials.

12. The method according to claim 11 , wherein the one or more semiconductor materials includes polysilicon.

13. The method according to claim 1 , wherein a channel layer of the string of transistors includes the first channel layer and the second channel layer electrically coupled by the channel connector.

14. The method according to claim 9 , wherein the second gate dielectric structure includes a tunnel insulating layer, a charge storage layer, and a blocking insulating layer that are sequentially formed over the second channel layer.

15. The method according to claim 1 , wherein the second channel layer and the contact are made of an identical material.

16. A method for manufacturing a semiconductor device, comprising:
forming a first deck of memory cells including a plurality of first substrings of memory cells over a substrate of the semiconductor device, the first substrings having respective first channel structures that include first channel layers and first gate dielectric structures that extend along a vertical direction above the substrate;
forming an inter-deck structure including channel connectors in an insulating layer, the channel connectors being disposed above the respective first substrings, the channel connectors being separated and electrically isolated by the insulating layer, the channel connectors include first structures having first recessed regions and second structures that are formed by overfilling the first recessed regions, the second structures include respective second recessed regions; and
forming a second deck of memory cells including a plurality of second substrings of memory cells, the second substrings being stacked above the respective channel connectors and having respective second channel structures that include second channel layers and second gate dielectric structures that extend along the vertical direction, the channel connectors electrically coupling the respective first channel layers and the second channel layers and being disposed below the respective second gate dielectric structures, wherein
the second channel layers extend into the respective second recessed regions and contact side walls of the respective second recessed regions and respective upper surfaces of the second recessed regions are fully covered by contacts that are connected to the respective second channel layers, the contacts electrically coupling the respective second channel layers and the respective second structures.

17. The method according to claim 16 , wherein the second gate dielectric structures are adjacent to and disposed above the second structures, and are separated from the first structures via the second structures.

18. The method according to claim 16 , wherein:
the first structures are in contact with the first channel layers and have respective upper surfaces of the first recessed regions; and
the second structures are in contact with the second channel layers and have the respe

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhang Ruo Fang
• Wang Enbo
• Yang Haohao
• Xu Qianbing
• Hu Yushi
• Tao Qian

Classifications

• H10D64/037 Primary

  comprising charge-trapping insulators · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title