Three dimensional NAND memory device with common bit line for multiple NAND strings in each memory block

Patent metadata

Field	Value
Publication number	US-10224104-B2
Application number	US-201615078555-A
Country	US
Kind code	B2
Filing date	Mar 23, 2016
Priority date	Mar 23, 2016
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

Two vertical NAND strings can share a common bit line by providing two pairs of drain select transistors. Channels of each vertical NAND string containing an adjoining pair of drain select transistors are incorporated into a respective vertical semiconductor channel, which is adjoined to a respective drain region which is connected to the common bit line. The drain select transistors have mismatched threshold voltages at each level such that each vertical NAND string includes a level at which a respective drain select transistor has a higher threshold voltage than a counterpart drain select transistor for the other vertical NAND string at the same level. By turning on three drain select transistors out of four, only one vertical NAND string can be activated while the common bit line is biased at a suitable bias voltage. A programming operation or a read operation can be performed only on the activated NAND string.

First claim

What is claimed is:

1. A memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
a first vertical NAND string extending through the alternating stack, the first vertical NAND string comprising a first drain region and first memory cell charge storage transistors in a series connection with a first drain select transistor and a second drain select transistor;
a second vertical NAND string extending through the alternating stack, the second vertical NAND string comprising a second drain region and second memory cell charge storage transistors in a series connection with a third drain select transistor and a fourth drain select transistor; and
a common bit line electrically connected to the first and to the second drain regions, wherein the first vertical NAND string and the second vertical NAND string are located in a same memory block,

wherein:
a first electrically conductive layer among the electrically conductive layers comprises a first common gate electrode for the first drain select transistor and the third drain select transistor;
a second electrically conductive layer among the electrically conductive layers comprises a second common gate electrode for the second drain select transistor and the fourth drain select transistor; and
the first drain select transistor and the fourth drain select transistor have higher threshold voltages than threshold voltages of the second and third drain select transistors;

wherein:
a first vertical semiconductor channel including channels of the first memory cell charge storage transistors and channels of the first and second drain select transistors, and a second vertical semiconductor channel including channels of the second memory cell charge storage transistors and channels of the third and fourth drain select transistors;
the first drain region contacts an upper end of the first vertical semiconductor channel and the second drain region contacts an upper end of the second vertical semiconductor channel;
a first portion of the first vertical semiconductor channel laterally surrounded by the first common gate electrode has a greater dopant concentration than a second portion of the first vertical semiconductor channel laterally surrounded by the second common gate electrode;
a first portion of the second vertical semiconductor channel laterally surrounded by the first common gate electrode has a lesser dopant concentration than a second portion of the second vertical semiconductor channel laterally surrounded by the second common gate electrode;
the second portion of the first vertical semiconductor channel and the first portion of the second vertical semiconductor channel have a same dopant concentration as portions of the first and second vertical semiconductor channels that constitute channels of the first and second memory cell charge storage transistors; and
the first and the second vertical semiconductor channels are adjoined to a common horizontal semiconductor channel located on or in the substrate.

2. A memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
a first vertical NAND string extending through the alternating stack, the first vertical NAND string comprising a first drain region and first memory cell charge storage transistors in a series connection with a first drain select transistor and a second drain select transistor;
a second vertical NAND string extending through the alternating stack, the second vertical NAND string comprising a second drain region and second memory cell charge storage transistors in a series connection with a third drain select transistor and a fourth drain select transistor; and
a common bit line electrically connected to the first and to the second drain regions, wherein the first vertical NAND string and the second vertical NAND string are located in a same memory block,

wherein:
a first electrically conductive layer among the electrically conductive lavers comprises a first common gate electrode for the first drain select transistor and the third drain select transistor;
a second electrically conductive layer among the electrically conductive layers comprises a second common gate electrode for the second drain select transistor and the fourth drain select transistor; and
the first drain select transistor and the fourth drain select transistor have higher threshold voltages than threshold voltages of the second and third drain select transistors;

and wherein the memory device comprises at least one feature selected from:
a first feature that a first vertical semiconductor channel including channels of the first memory cell charge storage transistors and channels of the first and second drain select transistors, and a second vertical semiconductor channel including channels of the second memory cell charge storage transistors and channels of the third and fourth drain select transistors; or
a second feature that channel regions of the first, second, third, and fourth drain select transistors have a same dopant concentration, and charge trapping material portions within the first and fourth drain select gate transistors have a different trapped electrical charge density than charge trapping material portions within the second and third drain select gate transistors;
wherein:
the first memory cell charge storage transistors are in a series connection with a first source select transistor and a second source select transistor;
the second memory cell charge storage transistors are is in a series connection with a third source select transistor and a fourth source select transistor;
a third electrically conductive layer among the electrically conductive layers comprises a third common gate electrode for the first source select transistor and the third source select transistor;
a fourth electrically conductive layer among the electrically conductive layers comprises a fourth common gate electrode for the second source select transistor and the fourth source select transistor; and
the first source select transistor and the fourth source select transistor have higher threshold voltages than threshold voltages of the second and third source select transistors.

3. The memory device of claim 2 , wherein:
channel regions of the first, second, third, and fourth source select transistors have a same dopant concentration; and
charge trapping material portions within the first and fourth source select gate transistors have a different trapped electrical charge density than charge trapping material portions within the second and third source select gate transistors.

4. A method of programming the select gate transistors of the device of claim 3 , comprising increasing threshold voltages for the first source select transistor and the fourth source select transistor by injecting electrical charge to charge trapping material portions within the first and fourth source select gate transistors, while not injecting electrical charge to charge trapping material portions within the second and third source select gate transistors.

5. The method claim 4 , further comprising:
applying a first voltage to the first common gate electrode and a second voltage to the second common gate electrode, wherein the first voltage is between the threshold voltages of the first and third drain select transistors, and the second voltage is greater than the threshold voltages of the second and fourth drain select transistors, whereby the second, third, and fourth drain select transistors are turned on and the first drain select transistor is turned off;
applying a pass voltage to the electrically conductive layers which comprise control gate electrodes of the firs

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Chowdhury Murshed
• Liu Jin
• Zhang Yanli
• Lin Andrew
• Makala Raghuveer S
• Alsmeier Johann

Classifications

• H01L27/11524

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• G11C16/10

  Programming or data input circuits · CPC title