Vertical non-volatile memory device including plural word line stacks

Patent metadata

Field	Value
Publication number	US-9711188-B2
Application number	US-201615141967-A
Country	US
Kind code	B2
Filing date	Apr 29, 2016
Priority date	Jul 22, 2009
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A vertical non-volatile memory device includes a substrate, and a first stack of word lines and a second stack of word lines extending in a first direction on the substrate and separated from each other in a second direction perpendicular to the first direction. The device further includes first array lines extending in the second direction on the first and the second stack, and connected to word lines of the first and the second stack through at least two of first via contacts in a same level. The device further include first word select lines being in a same level and extending in the first direction, and connected to each of the first array lines through at least one of second via contacts. Ends of each of the first and the second stack have a form of stairs on the substrate.

First claim

What is claimed is:

1. A vertical non-volatile memory device comprising:
a substrate;
a first stack of word lines and a second stack of word lines extending in a first direction on the substrate, the first and the second stack separated from each other in a second direction perpendicular to the first direction;
first array lines extending in the second direction on the first and the second stack, each of the first array lines connected to word lines of the first and the second stack through at least two of first via contacts in a same level; and
first word select lines being in a same level and extending in the first direction, each of the first word select lines connected to each of the first array lines through at least one of second via contacts,
wherein ends of each of the first and the second stack have a form of stairs on the substrate.

2. The vertical non-volatile memory device of claim 1 , further comprising;
a third stack of word lines on the first stack and a fourth stack of word lines on the second stack;
second array lines extending in the second direction on the third and the fourth stack, each of the second array lines connected to word lines of the third and the fourth stack through at least two of first via contacts in a same level; and
second word select lines being in a same level and extending in the first direction, each of the second word select lines connected to each of the second array lines through at least one of second via contacts,
wherein the first and the second word select lines are disposed higher than the first to the fourth stack, and the second word select lines are disposed higher than the first word select lines.

3. The vertical non-volatile memory device of claim 2 , wherein the first and the second word select lines are overlapped in a direction perpendicular to a top surface of the substrate.

4. The vertical non-volatile memory device of claim 2 , wherein the first and the second array lines are disposed in a same level.

5. The vertical non-volatile memory device of claim 2 , wherein the second array lines are disposed higher than the first array lines.

6. The vertical non-volatile memory device of claim 2 , wherein the second array lines and the first word select lines are disposed in a same level.

7. A vertical non-volatile memory device comprising:
a substrate;
a first to a fourth word line stacked in a first to a fourth levels on the substrate;
first word select lines being in a fifth level on the first and second word lines and connected to the first and the second word line, respectively; and
second word select lines being in a sixth level on the first to the fourth word lines and connected to the third and the fourth word line, respectively,
wherein the fifth and sixth level are higher than the first to the fourth levels and the sixth level is higher than the fifth level,
wherein ends of a stack of the first to the fourth word lines have a form of stairs on the substrate.

8. The vertical non-volatile memory device of claim 7 , wherein the first and the second word select lines are overlapped in a direction perpendicular to a top surface of the substrate.

9. The vertical non-volatile memory device of claim 7 , further comprising;
a fifth to a eighth word line, the fifth and the sixth word line stacked sequentially and interposed between the second word line and the third word line, and the seventh and the eighth word line stacked sequentially and disposed on the fourth word line,
third word select lines being in the fifth level and connected to the fifth and the sixth word line, respectively; and
fourth word select lines being in the sixth level and connected to the seventh and the eighth word line, respectively.

10. The vertical non-volatile memory device of claim 9 ,
wherein the substrate having a first to a third region, first region is disposed between a second and a third region,
wherein the first to the eighth word line are extending in the first direction over the first through third region of the substrate and each is coupled to memory transistors in the first region,
wherein the first and the second word select lines are in the second region, and
wherein the third and the fourth word select lines are in the third region.

11. A vertical non-volatile memory device comprising:
a substrate having a first to a third region, the first region disposed between the second and the third region;
stacks of word lines extending in a first direction over the first through third region of the substrate, the stacks separated from each other in a second direction perpendicular to the first direction;
first array lines extending in the second direction on the stacks in the second region, each of the first array lines connected to word lines of a portion of the stacks through at least two of first connect contacts in a same level; and
second array lines extending in the second direction on the stacks in the third region, each of the second array lines connected to word lines of the rest of the stacks through at least two of first connect contacts in a same level,
wherein ends of each of the stacks have a form of stairs on the substrate.

12. The vertical non-volatile memory device of claim 11 , wherein each of the word lines is coupled to memory transistors distributed in a direction perpendicular to a top surface of the substrate in the first region.

13. The vertical non-volatile memory device of claim 11 , wherein the first and the second array lines are disposed in a same level.

14. The vertical non-volatile memory device of claim 11 , further comprising;
first word select lines extending in the first direction in the second region, each of the first word select lines connected to each of the first array lines through at least one of second connect contacts, and
second word select lines extending in the first direction in the third region, each of the second word select lines connected to each of the second array lines through at least one of second connect contacts.

15. The vertical non-volatile memory device of claim 14 , wherein the stacks comprise a first to a fourth stack, and the first to the fourth stack are separated from each other in the second direction sequentially,
wherein each of the first array lines is connected to word lines of the first stack and the third stack in a same level, and each of the second array lines is connected to word lines of the second stack and the fourth stack in the same level.

16. The vertical non-volatile memory device of claim 14 , wherein the first word select lines comprise a stack of coplanar word select lines, and the second word select lines comprise a stack of coplanar word select lines.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Sung-Min
• Kim Han-Soo
• Cho Won-Seok
• Jang Jae-Hoon
• Shim Sun-Il
• Jeong Jae-Hun
• Kim Ki-Hyun

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H01L27/115

  Electricity · mapped topic

• G11C5/06 Primary

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• H01L27/112

  Electricity · mapped topic

• H01L27/11517

  Electricity · mapped topic