Land side and die side cavities to reduce package Z-height

Patent metadata

Field	Value
Publication number	US-9293426-B2
Application number	US-201213631669-A
Country	US
Kind code	B2
Filing date	Sep 28, 2012
Priority date	Sep 28, 2012
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a package substrate having a plurality of buildup layers;
a die mounted to a die side of the package substrate, wherein the die has a die cavity in an active surface of the die, wherein the die is mounted to the package substrate via bumps within the die cavity;
a cavity in one or more buildup layers; and
a capacitor mounted within the cavity wherein said capacitor is not in vertical alignment to said die.

2. The semiconductor device of claim 1 , further comprising a printed circuit board (PCB), wherein the PCB has a first surface mounted to a land side of the package substrate.

3. The semiconductor device of claim 1 , wherein the package substrate further comprises a core on which the plurality of buildup layers is formed.

4. The semiconductor device of claim 1 , wherein the die is mounted within a second cavity in the package substrate.

5. The semiconductor device of claim 1 , further comprising a second cavity formed within one or more buildup layers, wherein a second capacitor is mounted within the second cavity.

6. The semiconductor device of claim 1 , wherein the capacitor protrudes from the surface of the package substrate.

7. The semiconductor device of claim 1 , wherein the capacitor does not protrude from the surface of the package substrate.

8. The semiconductor device of claim 2 , further comprising a plurality of solder balls mounting the PCB to the land side of the package substrate, wherein each of the plurality of solder balls is mounted within a land side cavity in one or more buildup layers on the land side of the package substrate.

9. The semiconductor device of claim 2 , further comprising a plurality of solder balls mounting the PCB to the land side of the package substrate, wherein each of the plurality of solder balls is mounted within a PCB cavity in one or more buildup layers of the PCB.

10. The semiconductor device of claim 2 , further comprising a plurality of solder balls mounting the PCB to the land side of the package substrate, wherein each of the plurality of solder balls is mounted within a land side cavity in one or more buildup layers on the land side of the package substrate and within a PCB cavity in one or more buildup layers of the PCB.

11. The semiconductor device of claim 2 , further comprising a second package substrate having a land side mounted to a second surface of the PCB, wherein the second surface of the PCB is opposite the first surface of the PCB.

12. The semiconductor device of claim 11 , wherein the second package substrate comprises a plurality of buildup layers, and wherein a second capacitor is mounted in second cavity within one or more of the buildup layers.

13. A device, comprising:
a PCB having a first surface;
a first package mounted to the first surface, the first package comprising:
a package substrate having a die side surface and a land side surface;
a die mounted to the package substrate; and
a capacitor mounted within a cavity in the package substrate wherein

the capacitor is not in vertical alignment to the die;
a second package mounted to a second surface of the PCB, wherein the second surface is opposite the first surface; and
a plurality of solder balls mounting the land side of the package substrate to the PCB.

14. The device of claim 13 , wherein the cavity is formed in the die side surface of the package substrate.

15. The device of claim 14 , wherein the package substrate comprises a plurality of buildup layers, and wherein the cavity extends through one or more buildup layers.

16. The device of claim 14 , wherein the cavity is formed in the land side surface of the package substrate.

17. The device of claim 16 , wherein the package substrate comprises a plurality of buildup layers, and wherein the cavity extends through one or more buildup layers.

18. The device of claim 13 , wherein the die is mounted in a cavity formed in the die side surface of the package substrate.

19. The device of claim 13 , wherein each solder ball is mounted within a land side cavity formed within the land side surface of the package substrate.

20. The device of claim 13 , wherein each solder ball is mounted within a PCB cavity formed within the first surface of the PCB.

21. The device of claim 13 , wherein each solder ball is mounted within a land side cavity formed within the land side surface of the package substrate and a PCB cavity formed within the first surface of the PCB.

22. A semiconductor device;
a package substrate having a plurality of build up layers, the package substrate having a die side and a land side;
a die mounted to the die side of the package substrate, wherein the die has a die cavity in an active surface of the die, wherein the die is mounted to the package substrate via bumps within the die cavity; and
a cavity in one or more build up layers on the die side of the package substrate; and
a capacitor mounted within the cavity.

23. The semiconductor device comprising:
a package substrate having a plurality of build up layers, the package substrate having a die side and a land side;
a die mounted to the die side of the package substrate;
a cavity in one or more build up layers of the package substrate;
a capacitor mounted within the cavity;
a printed circuit board (PCB) wherein the PCB has a first surface mounted to the land side of the package substrate by a plurality of solder balls; and
a second package substrate having a land side mounted to a second surface of the PCB, wherein the second surface of the PCB is opposite the first surface of the PCB.

24. A device, comprising:
a PCB having a first surface;
a first package mounted to the first surface, the first package comprising:
a package substrate having a die side surface and a land side surface;
a die mounted to the package substrate; and
a capacitor mounted within a cavity in the package substrate;

a plurality of solder balls mounting the land side of the package substrate to the PCB; and
a second package mounted to a second surface of the PCB, wherein the second surface is opposite the first surface.

25. A semiconductor device, comprising:
a package substrate having a plurality of buildup layers;
a die wherein the die mounted to a die side of the package substrate;
a cavity in one or more buildup layers;
a capacitor mounted within the cavity wherein said capacitor is not in vertical alignment to said die;
a printed circuit board (PCB), wherein the PCB has a first surface mounted to a land side of the package substrate; and
a second package substrate having a land side mounted to a second surface of the PCB, wherein the second surface of the PCB is opposite the first surface of the PCB.

26. The semiconductor device of claim 25 , wherein the second package substrate comprises a plurality of buildup layers, and wherein a second capacitor is mounted in second cavity within one or more of the buildup layers.

Assignees

• Hossain Md Altaf
• Gilbert Scott A
• Intel Corp

Inventors

• Hossain Md Altaf
• Gilbert Scott A

Classifications

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title