Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures

Patent metadata

Field	Value
Publication number	US-11798999-B2
Application number	US-202217873885-A
Country	US
Kind code	B2
Filing date	Jul 26, 2022
Priority date	Nov 16, 2018
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

Methods for forming a metal silicate film on a substrate in a reaction chamber by a cyclical deposition process are provided. The methods may include: regulating the temperature of a hydrogen peroxide precursor below a temperature of 70° C. prior to introduction into the reaction chamber, and depositing the metal silicate film on the substrate by performing at least one unit deposition cycle of a cyclical deposition process. Semiconductor device structures including a metal silicate film formed by the methods of the disclosure are also provided.

First claim

What is claimed is:

1. A semiconductor device structure comprising:
a silicon germanium channel region;
an interface layer comprising a metal silicate film disposed on the silicon germanium channel region, wherein the metal silicate film comprises a halide level of less than about 0.2 atomic-%; and
a high-k dielectric material disposed on the interface layer.

2. The semiconductor device structure of claim 1 , wherein the metal silicate film comprises at least one of hafnium silicate, yttrium silicate, zirconium silicate, aluminum silicate, scandium silicate, cerium silicate, erbium silicate, or strontium silicate.

3. The semiconductor device structure of claim 1 , wherein the metal silicate film has an atomic percentage of silicon between approximately 10 atomic-% and approximately 60 atomic-%.

4. The semiconductor device structure of claim 1 , wherein the metal silicate film has an atomic percentage of silicon between approximately 10 atomic-% and approximately 30 atomic-%.

5. The semiconductor device structure of claim 1 , wherein the metal silicate film has an atomic percentage of silicon less than 10 atomic-%.

6. The semiconductor device structure of claim 1 , wherein the high-k dielectric material comprises a metallic oxide having a dielectric constant greater than approximately 7.

7. The semiconductor device structure of claim 1 , wherein the metal silicate film has an effective oxide charge density of less than 5 e 10 cm −2 .

8. The semiconductor device structure of claim 1 , wherein an interface trap density at an interface between the silicon germanium channel region and the interface layer is less than about 7 e 12 cm −2 eV −1 .

9. A semiconductor device structure, comprising:
a silicon germanium channel region;
an interface layer comprising a metal silicate film disposed on the silicon germanium channel region, wherein the metal silicate film has an atomic percentage of silicon between approximately 10 atomic-% and approximately 60 atomic-%; and
a high-k dielectric material disposed on the interface layer.

10. The semiconductor device structure of claim 9 , wherein the metal silicate film has an effective oxide charge density of less than 5 e 10 cm −2 .

11. The semiconductor device structure of claim 9 , wherein the metal silicate film comprises at least one of hafnium silicate, yttrium silicate, zirconium silicate, aluminum silicate, scandium silicate, cerium silicate, erbium silicate, or strontium silicate.

12. The semiconductor device structure of claim 9 , wherein silicon germanium comprised in the silicon germanium channel region is represented by Si 1−x Ge x , wherein x is between approximately 0 and approximately 0.50.

13. The semiconductor device structure of claim 9 , further comprising at least two source regions, wherein the silicon germanium channel region is disposed between the at least two source regions.

14. The semiconductor device structure of claim 13 , wherein the at least two source regions comprise a phosphorus doped silicon film.

15. The semiconductor device structure of claim 14 , further comprising a gate electrode disposed on the high-k dielectric material, wherein the gate electrode comprises at least one of a metal, a metal nitride, or a metal carbide.

16. A semiconductor device structure, comprising:
a silicon germanium channel region;
an interface layer comprising a metal silicate film disposed on the silicon germanium channel region, wherein the metal silicate film comprises a carbon impurity level of less than 1 atomic-%; and
a high-k dielectric material disposed on the interface layer.

17. The semiconductor device structure of claim 16 , wherein the metal silicate film comprises a hydrogen impurity level of less than 5 atomic-%.

18. The semiconductor device structure of claim 16 , wherein the metal silicate film has an atomic percentage of silicon between approximately 10 atomic-% and approximately 60 atomic-%.

19. The semiconductor device structure of claim 18 , wherein the metal silicate film comprises aluminum silicate.

20. The semiconductor device structure of claim 16 , wherein the metal silicate film comprises less than about 0.2 atomic-% halide.

Assignees

• Asm Ip Holding Bv

Inventors

• Tang Fu
• Hsu Peng-Fu
• Givens Michael Eugene
• Xie Qi

Classifications

• H10P14/6929

  the material containing aluminium, e.g. AlSiOx · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/668

  the materials being characterised by the deposition precursor materials · CPC title

• H10P14/662

  Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548) · CPC title

• H10D64/01332

  Making the insulator · CPC title