Nonvolatile memory device having cell-over-periphery (COP) structure with address re-mapping

Patent metadata

Field	Value
Publication number	US-11797405-B2
Application number	US-202217935502-A
Country	US
Kind code	B2
Filing date	Sep 26, 2022
Priority date	Sep 27, 2019
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

First claim

What is claimed is:

1. A nonvolatile memory device, comprising:
a substrate having a plurality of address decoders and a plurality of page buffer circuits therein;
a memory cell array comprising:
a first vertical structure having a plurality of first memory sub-blocks therein and a first plurality of through-hole vias extending at least partially therethrough; and
a second vertical structure having a plurality of second memory sub-blocks therein and a second plurality of through-hole vias extending at least partially therethrough; and
a control circuit configured to group the first memory sub-blocks into a plurality of first groups of memory sub-blocks such that each of the plurality of first groups of memory sub-blocks are disposed between two adjacent through-hole vias from among the first plurality of through-hole vias without any through hall vias disposed therebetween, and a defective one of the first memory sub-blocks is remapped to a non-defective one of the first memory sub-blocks, wherein the non-defective one of the first memory sub-blocks and the defective one of the first memory sub-blocks are included in the same group of memory sub-blocks among the plurality of first groups of memory sub-blocks.

2. The nonvolatile memory device of claim 1 , wherein the control circuit is further configured to group the second memory sub-blocks into a plurality of second groups of memory sub-blocks such that each of the plurality of second groups of memory sub-blocks are disposed between two adjacent through-hole vias from among the second plurality of through-hole vias without any through hall vias disposed therebetween, and a defective one of the second memory sub-blocks is remapped to a non-defective one of the second memory sub-blocks, wherein the non-defective one of the second memory sub-blocks and the defective one of the second memory sub-blocks are included in the same group of memory sub-blocks from among the plurality of second groups of memory sub-blocks.

3. The nonvolatile memory device of claim 1 , wherein:
the memory cell array includes a plurality of mats corresponding to different bit-lines of a plurality of bit-lines; and
each of the plurality of mats includes the first vertical structure and the second vertical structure.

4. The nonvolatile memory device of claim 1 , wherein the control circuit is further configured to control the plurality of address decoders and the plurality of page buffer circuits within the substrate, in response to a command and address received by the nonvolatile memory device.

5. The nonvolatile memory device of claim 4 , wherein the control circuit comprises:
a register configured to store boundary address information associated with the first plurality of through-hole vias;
a group information generator configured to generate group address information indicating a group to which the first memory sub-block associated with the address belongs to, based on the address and the boundary address information; and
an address re-mapper configured to generate a first re-mapped address to access the non-defective one of the first memory sub-blocks by re-mapping an address associated with the defective one of the first memory sub-blocks, based on the group address information.

6. The nonvolatile memory device of claim 4 , wherein the first and second vertical structures having a plurality of bit lines thereon and a plurality of word lines therein; wherein at least some of the first plurality of through-hole vias electrically connect at least some of the bit lines to portions of the plurality of page buffer circuits; and wherein at least some of the first plurality of through-hole vias electrically connect at least some of the word lines to portions of the plurality of address decoders.

7. A nonvolatile memory device, comprising:
a memory cell region including a memory cell array therein, which comprises a first vertical structure and a second vertical structure, the first vertical structure including a plurality of first memory sub-blocks therein, and a first plurality of through-hole vias extending at least partially therethrough, the second vertical structure including a plurality of second memory sub-blocks therein, and a second plurality of through-hole vias extending at least partially therethrough; and
a control circuit configured to group the first memory sub-blocks into a plurality of first groups of memory sub-blocks such that each of the plurality of first groups of memory sub-blocks are disposed between two adjacent through-hole vias from among the first plurality of through-hole vias without any through hole vias disposed therebetween, and a defective one of the first memory sub-blocks is remapped to a non-defective one of the first memory sub-blocks, wherein the non-defective one of the first memory sub-blocks and the defective one of the first memory sub-blocks are included in the same group of memory sub-blocks among the plurality of first groups of memory sub-blocks.

8. The nonvolatile memory device of claim 7 , wherein the control circuit is further configured to group the second memory sub-blocks into a plurality of second groups of memory sub-blocks such that each of the plurality of second groups of memory sub-blocks are disposed between two adjacent through-hole vias from among the second plurality of through-hole vias without any through hole vias disposed therebetween, and a defective one of the second memory sub-blocks is remapped to a non-defective one of the second memory sub-blocks, wherein the non-defective one of the second memory sub-blocks and the defective one of the second memory sub-blocks are included in the same group of memory sub-blocks among the plurality of second groups of memory sub-blocks.

9. The nonvolatile memory device of claim 7 , further comprising a peripheral circuit region under the memory cell region, the peripheral circuit region having a plurality of address decoders and a plurality of page buffer circuits therein; and wherein an interface between the peripheral circuit region and the memory cell region extends between the plurality of address decoders and the plurality of page buffer circuits and the memory cell array.

10. The nonvolatile memory device of claim 7 , wherein:
the memory cell array includes a plurality of mats corresponding to different bit-lines of a plurality of bit-lines; and
each of the plurality of mats includes the first vertical structure and the second vertical structure.

11. The nonvolatile memory device of claim 7 , wherein the memory cell region further comprises:
a plurality of word-lines extending in a first direction; and
a plurality of bit-lines extending in a second direction crossing the first direction.

12. A nonvolatile memory device comprising:
a memory cell region including a plurality of word-lines extending in a first direction, a plurality of bit-lines extending in a second direction and a memory cell array therein, wherein the memory cell array includes a first vertical structure and a second vertical structure adjacent to each other in the first direction, wherein the first vertical structure includes a plurality of first memory sub-blocks and a first plurality of through-hole vias extending at least partially therethrough and the second vertical structure includes a plurality of second memory sub-blocks corresponding to the first memory sub-blocks and a second plurality of through-hole vias extending at least partially therethrough;
a peripheral circuit region under the memory cell region, wherein the peripheral circuit region includes a lower substrate that includes a plurality of address decoders and a plurality of page buffer circuits which co

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Yonghyuk
• Nam Sangwan
• Yu Jaeduk
• Park Sangwon
• Lim Bongsoon

Classifications

• G06F11/2094 Primary

  Redundant storage or storage space (G06F11/2056 takes precedence) · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G06F2201/85

  Active fault masking without idle spares · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title