Data processing method, apparatus, and system

Patent metadata

Field	Value
Publication number	US-9727253-B2
Application number	US-201514812747-A
Country	US
Kind code	B2
Filing date	Jul 29, 2015
Priority date	Jul 30, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A data processing method, including dividing a to-be-processed data block into multiple data subblocks, where a quantity of the multiple data subblocks is less than or equal to a quantity of banks Banks of a memory, and performing an access operation on a bank corresponding to each data subblock of the to-be-processed block, where different data subblocks of the block are corresponding to different Banks of the memory. In an embodiment of the present disclosure, a processor maps different data subblocks of a to-be-processed Block to different Banks, so that a quantity of inter-page access operations on a same Block may be reduced, thereby improving memory access efficiency when two contiguous memory access operations access different pages of a same bank.

First claim

What is claimed is:

1. A data processing method, wherein the method comprises:
determining a to-be-processed data block according to a preset data block size and a memory access instruction, wherein the preset data block size is a product of the quantity of banks of the memory, a memory data bit width, one burst length, and a quantity of bursts;
dividing the to-be-processed data block into multiple data subblocks according to a preset data subblock size, wherein the preset data subblock size is a product of the memory data bit width, the one burst length, and the quantity of bursts, and wherein a quantity of the multiple data subblocks is less than or equal to a quantity of banks of a memory; and
accessing a bank corresponding to each data subblock of the to-be-processed data block, wherein different data subblocks of the to-be-processed data block are corresponding to different banks of the memory.

2. The method according to claim 1 , wherein performing the access operation on the bank corresponding to each data subblock of the to-be-processed data block comprises:
determining, according to a bank access sequence corresponding to another data block that is accessed before the to-be-processed data block is accessed and a correspondence between each data subblock of the to-be-processed data block and a bank of the memory, a bank access sequence corresponding to the to-be-processed data block; and
accessing, according to the bank access sequence corresponding to the to-be-processed data block, the bank corresponding to each data subblock of the to-be-processed data block, so that a time interval between two times of access to the same bank of the memory is the longest.

3. The method according to claim 1 , wherein determining the to-be-processed data block according to the preset data block size and the memory access instruction comprises determining, based on the preset data block size, each to-be-processed data block for to-be-processed data indicated by the memory access instruction.

4. The method according to claim 1 , wherein after dividing the to-be-processed data block into the multiple data subblocks, the method further comprises mapping the multiple data subblocks successively to banks of the memory that are numbered in ascending or descending order.

5. A data processing apparatus, comprising:
a processor configured to:
determine a to-be-processed data block according to a preset data block size and a memory access instruction, wherein the preset data block size is a product of the quantity of banks of the memory, a memory data bit width, one burst length, and a quantity of bursts;
divide the to-be-processed data block into multiple data subblocks according to a preset data subblock size, wherein the preset data subblock size is a product of the memory data bit width, the one burst length, and the quantity of bursts, and wherein a quantity of the multiple data subblocks is less than or equal to a quantity of banks of a memory; and
perform an access operation on a bank corresponding to each data subblock of the to-be-processed data block, wherein different data subblocks of the to-be-processed data block are corresponding to different banks of the memory.

6. The apparatus according to claim 5 , wherein the processor is further configured to:
determine, according to a bank access sequence corresponding to another data block that is accessed before the to-be-processed data block is accessed and a correspondence between each data subblock of the to-be-processed data block and a bank of the memory, a bank access sequence corresponding to the to-be-processed data block; and
access, according to the bank access sequence corresponding to the to-be-processed data block, the bank corresponding to each data subblock of the to-be-processed data block, so that a time interval between two times of access to the same bank of the memory is the longest.

7. The apparatus according to claim 5 , wherein the processor is configured to determine, based on the preset data block size, each to-be-processed data block for to-be-processed data indicated by the memory access instruction.

8. The apparatus according to claim 5 , wherein the processor is further configured to map the multiple data subblocks successively to banks of the memory that are numbered in ascending or descending order.

9. A data processing system, wherein the system comprises:
a processor;
a data line; and
a memory, wherein the memory comprises multiple banks, wherein when the system operates, the processor communicates with the memory through the data line, and wherein the processor is configured to:
determine a to-be-processed data block according to a preset data block size and a memory access instruction, wherein the preset data block size is a product of the quantity of banks of the memory, a memory data bit width, one burst length, and a quantity of bursts;
divide the to-be-processed data block into multiple data subblocks according to a preset data subblock size, wherein the preset data subblock size is a product of the memory data bit width, the one burst length, and the quantity of burst, and wherein a quantity of the multiple data subblocks is less than or equal to a quantity of banks of the memory; and
perform an access operation on a bank corresponding to each data subblock of the to-be-processed data block, wherein different data subblocks of the to-be-processed data block are corresponding to different banks of the memory.

10. The system according to claim 9 , wherein the processor is configured to:
determine, according to a bank access sequence corresponding to another data block that is accessed before the to-be-processed data block is accessed and a correspondence between each data subblock of the to-be-processed data block and a bank of the memory, a bank access sequence corresponding to the to-be-processed data block; and
access, according to the bank access sequence corresponding to the to-be-processed data block, the bank corresponding to each data subblock of the to-be-processed data block, so that a time interval between two times of access to the same bank of the memory is the longest.

11. The system according to claim 9 , wherein the processor is configured to determine, based on the preset data block size, each to-be-processed data block for to-be-processed data indicated by the memory access instruction.

12. The system according to claim 9 , wherein the processor is further configured to map the multiple data subblocks successively to banks of the memory that are numbered in ascending or descending order.

Assignees

• Huawei Tech Co Ltd
• Huawei Tech Co Ltd

Inventors

• Kong Chao
• Cao Xiangming
• Xu Zhenghua

Classifications

• G06F13/161 Primary

  with latency improvement · CPC title

• G06F3/0611 Primary

  in relation to response time · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/064

  Management of blocks · CPC title