Nonvolatile memory device having cell-over-periphery (COP) structure with address re-mapping

Patent metadata

Field	Value
Publication number	US-11467932-B2
Application number	US-202016865948-A
Country	US
Kind code	B2
Filing date	May 4, 2020
Priority date	Sep 27, 2019
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

First claim

What is claimed is:

1. A nonvolatile memory device, comprising:
a lower substrate having address decoder and page buffer circuitry therein;
first and second upper substrates on the lower substrate;
a memory cell array comprising:
a first vertical structure on the first upper substrate, the first vertical structure having a plurality of first memory sub-blocks therein and a first plurality of through-hole vias extending at least partially therethrough; and
a second vertical structure on the second upper substrate, the second vertical structure having a plurality of second memory sub-blocks therein and a second plurality of through-hole vias extending at least partially therethrough; and

a control circuit configured to group the first memory sub-blocks into a plurality of groups of memory sub-blocks according to their closeness to the first plurality of through-hole vias, and perform address re-mapping by replacing a defective one of the first memory sub-blocks with a non-defective one of the first memory sub-blocks, subject to a constraint that the non-defective one of the first memory sub-blocks is selected as a replacement based on its inclusion in the same group of memory blocks as the defective one of the first memory sub-blocks.

2. The nonvolatile memory device of claim 1 , wherein the control circuit is further configured to control the address decoder and page buffer circuitry within the lower substrate, in response to a command and address received by the nonvolatile memory device.

3. The nonvolatile memory device of claim 2 , wherein the control circuit comprises:
a register configured to store boundary address information associated with the first plurality of through-hole vias;
a group information generator configured to generate group address information indicating a group to which the first memory sub-block associated with the address belongs to, based on the address and the boundary address information; and
an address re-mapper configured to generate a first re-mapped address to access the non-defective one of the first memory sub-blocks by re-mapping an address associated with the defective one of the first memory sub-blocks, based on the group address information.

4. The nonvolatile memory device of claim 2 , wherein the first and second vertical structures having a plurality of bit lines thereon and a plurality of word lines therein; wherein at least some of the first plurality of through-hole vias electrically connect at least some of the bit lines to portions of the page buffer circuitry; and wherein at least some of the first plurality of through-hole vias electrically connect at least some of the word lines to portions of the address decoder circuitry.

5. The nonvolatile memory device of claim 1 , wherein the first vertical structure has a plurality of channel holes of unequal diameter therein; and wherein the diameters of the channel holes vary according to their respective position within the first vertical structure.

6. A nonvolatile memory device, comprising:
a first semiconductor substrate having a memory cell array thereon, which comprises a first vertical structure, the first vertical structure including a plurality of first memory sub-blocks therein, and a first plurality of through-hole vias extending at least partially therethrough; and
a control circuit configured to: (i) group the first memory sub-blocks into a plurality of groups of memory sub-blocks according to their threshold voltage characteristics, which are a function of their relative physical location within the first vertical structure, and (ii) perform address re-mapping by replacing a defective one of the first memory sub-blocks with a non-defective one of the first memory sub-blocks, subject to a constraint that the non-defective one of the first memory sub-blocks is selected as a replacement based on its inclusion in the same group of memory blocks as the defective one of the first memory sub-blocks.

7. The nonvolatile memory device of claim 6 , wherein the nonvolatile memory device has a cell-over-periphery (COP) structure, which comprises a second semiconductor layer having address decoder and page buffer circuitry therein; and wherein an interface between the second semiconductor layer and the first semiconductor substrate extends between the address decoder and page buffer circuitry and the memory cell array.

8. The nonvolatile memory device of claim 7 , wherein the memory cell array has a plurality of channel holes of unequal diameter therein; and wherein the diameters of the channel holes vary according to their respective position within the memory cell array.

9. The nonvolatile memory device of claim 6 , wherein the memory cell array has a plurality of channel holes of unequal diameter therein; and wherein the diameters of the channel holes vary according to their respective position within the memory cell array.

10. The nonvolatile memory device of claim 9 , wherein nonvolatile memory cells within the memory cell array have a gate-all-around structure.

11. A nonvolatile memory device comprising:
a first semiconductor layer including a plurality of word-lines extending in a first direction, a plurality of bit-lines extending in a second direction, first and second upper substrates adjacent to each other in the first direction and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, wherein the first vertical structure includes a plurality of first sub-blocks and the second vertical structure includes a plurality of second sub-blocks corresponding to the first sub-blocks;
a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, wherein the second semiconductor layer includes a lower substrate that includes a plurality of address decoders and a plurality of page buffer circuits which control the memory cell array; and
a control circuit configured to control the address decoders and the page buffer circuits based on a command an address from an outside,
wherein the first vertical structure includes first via areas in which one or more through-hole vias are provided and the first via areas are spaced apart in the second direction, wherein the one or more through-hole vias pass through the first vertical structure, and the second vertical structure includes second via areas corresponding to the first via areas,
wherein the first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas,
wherein the first sub-blocks and the second sub-blocks constitute memory blocks, and
wherein the control circuit is configured to group the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and configured to perform address re-mapping such that at least one sub-block of a second memory block in a first group is selected in response to a defect occurring in a first memory block in a first group of the plurality of groups.

12. The nonvolatile memory device of claim 11 , wherein when the first memory block includes a first sub-block and a second sub-block, the control circuit is configured to perform the address re-mapping such that the second sub-block of the first memory block is replaced with a second sub-block of the second memory block in response to a defect occurring in the second sub-block of the first memory block.

13. The nonvolatile memory device of claim 11 , wherein the control circuit is configured to perform the address re-mapping such that t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Yonghyuk
• Nam Sangwan
• Yu Jaeduk
• Park Sangwon
• Lim Bongsoon

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G06F11/2094 Primary

  Redundant storage or storage space (G06F11/2056 takes precedence) · CPC title