Dynamic memory recovery at the sub-block level

Patent metadata

Field	Value
Publication number	US-9659666-B2
Application number	US-201514841046-A
Country	US
Kind code	B2
Filing date	Aug 31, 2015
Priority date	Aug 31, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A non-volatile flash memory has bit lines spanning multiple blocks grouped into columns, where each block is connected along multiple regular columns and one or more redundancy columns. When there is a local column defect, so that the defect is not at the level of the whole block or global column, the portions of a column at an individual block can be remapped to a portion of the same block along a redundant column. Sections of multiple columns from different blocks can be remapped to the same redundancy column. Then a memory block includes a number of independently accessible sub-blocks, the process can also be implemented at the sub-block level. A dynamic, system level implementation is presented.

First claim

It is claimed:

1. A method of operating a memory system, comprising:
determining that a portion of a first sub-block of a first block along a first regular column is defective, where the memory system includes a memory circuit that includes an array having a plurality of blocks, each block having a plurality of individually selectable sub-blocks of a plurality of non-volatile memory cells spanned by a plurality of access columns and where each sub-block of a block is selectable by a common select signal independently of other sub-blocks of the block, and wherein each access column is formed of a plurality of N adjacent bit lines along which the memory cells of the sub-blocks are connectable to sensing circuitry, the access columns including a plurality of regular columns and one or more redundancy columns; and
in response to determining that the portion of the first sub-block along the first regular column is defective, remapping the portion of the first sub-block along the first regular column to a portion of the first sub-block along a first redundancy column,
wherein neither a portion of sub-blocks of the first block other than the first sub-block along the first regular column nor a portion of blocks other than the first block along the first regular column are remapped in response thereto.

2. The method of claim 1 , wherein the memory system further includes a controller, and the determining that a portion of the first sub-block of the first block along the first regular column is defective is in response to an operation scheduled by the controller.

3. The method of claim 1 , further comprising:
determining that a portion of a second sub-block along a second regular column is defective; and
in response to determining that the portion of the second sub-block along the second regular column is defective, remapping the portion of the second sub-block along the second regular column to a portion of the second sub-block along the first redundancy column, wherein the portion of sub-blocks other than the second sub-block along the second regular column are not remapped in response thereto.

4. The method of claim 3 , wherein the second sub-block is a sub-block of the first block.

5. The method of claim 3 , wherein the second sub-block is not a sub-block of the first block.

6. The method of claim 4 , wherein the first and second regular columns are the same.

7. The method of claim 4 , wherein the first and second regular columns are different.

8. The method of claim 1 , wherein the memory system further includes a controller and the determining that the portion of the first sub-block along the first regular column is defective is performed in response to a read error result as determined by the controller.

9. The method of claim 1 , wherein the memory system further includes a controller and the controller maintains in non-volatile memory a copy of information on the remapping.

10. The method of claim 1 , wherein the memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.

11. A method of operating a memory system, comprising:
receiving by the memory system a request to read a first page of data, where the memory system includes a memory circuit that includes an array having a plurality of blocks, each block having a plurality of individually selectable sub-blocks of non-volatile memory cells spanned by a plurality of access columns and where each sub-block of a block is selectable by a common select signal independently of other sub-blocks of the block, and wherein each access column is formed of a plurality of N adjacent bit lines along which the memory cells of the blocks are connectable to sensing circuitry, the access columns including a plurality of regular columns and one or more redundancy columns;
determining that the first page of data corresponds to a first sub-block in which a portion thereof along a first regular column is remapped to a portion of the first sub-block along a first redundancy column, wherein the remapping for the first sub-block along the first regular column is remapped independently of portions of other sub-blocks along the first regular column; and
providing the first page of data, wherein the data corresponding to the first regular column of the first sub-block is provided from the first redundancy column of the first sub-block.

12. The method of claim 11 , wherein the memory system further including a controller and the memory circuit receives the request to read the first page of data from the controller, wherein the memory circuit provides the controller with the first page of data where the data corresponding to the first regular column of the first sub-block is replaced from the first redundancy column of the first sub-block.

13. The method of claim 11 , wherein the memory system further including a controller and the memory circuit receives the request to read the first page of data from the controller,
wherein, in response to the request to read the first page of data, the memory circuit transfers to the controller a read result from the first regular column and the first redundancy column to the controller and the determining and providing are performed by the controller.

14. The method of claim 11 , further comprising:
receiving a request to read a second page of data;
determining that the second page of data corresponds to a second sub-block in which a portion thereof along a second regular column is remapped to a portion of the second sub-block along a first redundancy column, wherein the second sub-block is different that the first sub-block and the remapping for the second sub-block along the second regular column is remapped independently of portions of other sub-blocks along the second regular column; and
providing the second page of data, wherein the data corresponding to the second regular column of the second sub-block is provided from the first redundancy column of the second sub-block.

15. The method of claim 11 , wherein the first and second regular column are the same.

16. The method of claim 11 , wherein the first and second regular column are different.

17. The method of claim 11 , wherein the memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.

18. A non-volatile memory system comprising:
an array having a plurality of blocks, each block having a plurality of individually selectable sub-blocks of non-volatile memory cells spanned by a plurality of access columns, where each sub-block of a block is selectable by a common select signal independently of other sub-blocks of the block, and wherein each access column is formed of a plurality of N adjacent bit lines along which the memory cells of the blocks are connectable to sensing circuitry, the access columns including a plurality of regular columns and one or more redundancy columns; and
logic circuitry to control access to the array, wherein the logic circuitry is configured to independently remap portions of sub-blocks along the regular columns to the portion of the same sub-block along a first of the redundancy columns such that remapped regular column of each of the sub-blocks is distinct.

19. The non-volatile memory system of claim 18 , wherein the memory system includes a memory circuit on which the array and logic circuitry are f

Assignees

• Sandisk Technologies Llc

Inventors

• Yang Niles Nian
• Avila Chris

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/3404 Primary

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C29/76

  using address translation or modifications · CPC title