Metal oxide semiconductor field-effect transistor (MOSFET) devices and manufacturing methods thereof

Patent metadata

Field	Value
Publication number	US-11791394-B2
Application number	US-202218053777-A
Country	US
Kind code	B2
Filing date	Nov 9, 2022
Priority date	Apr 28, 2020
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

Provided are metal oxide field-effect transistor (MOSFET) devices having a metal gate structure, in which a work function of the metal gate structure is uniform along a length direction of a channel, and manufacturing methods thereof. The MOSFET devices include a semiconductor substrate, an active area on the semiconductor substrate and extending in a first direction, and a gate structure on the semiconductor substrate. The gate structure extends across the active area in a second direction that traverses the first direction and comprises a high-k layer, a first metal layer, a work function control (WFC) layer, and a second metal layer, which are sequentially stacked on the active area. A lower surface of the WFC layer may be longer than a first interface between a lower surface of the first metal layer and an upper surface of the high-k layer in the first direction.

First claim

What is claimed is:

1. A manufacturing method of a metal oxide semiconductor field-effect transistor (MOSFET) device, the manufacturing method comprising:
forming an active area having a fin shape, protruding from a semiconductor substrate and extending in a first direction;
forming, on the semiconductor substrate, a dummy gate structure extending in a second direction that traverses the first direction and covering a portion of the active area;
forming two spacers respectively on side surfaces of the dummy gate structure, the side surfaces of the dummy gate structure being spaced apart from each other in the first direction;
removing the dummy gate structure between the two spacers;
forming a high-k layer between the two spacers;
etching inner side surfaces of the two spacers to increase distance between the two spacers;
forming a first metal layer on an upper surface of the high-k layer;
forming a work function control (WFC) layer on the first metal layer; and
forming a second metal layer on the WFC layer,
wherein a lower surface of the WFC layer is longer than a first interface between a lower surface of the first metal layer and the upper surface of the high-k layer in the first direction.

2. The manufacturing method of claim 1 , further comprising forming an interface layer,
wherein the high-k layer, the first metal layer, and the WFC layer are respectively formed only on an upper surface of the interface layer, the upper surface of the high-k layer, and an upper surface of the first metal layer, by anisotropic deposition.

3. The manufacturing method of claim 1 , wherein etching the inner side surfaces of the two spacers comprises etching the inner side surfaces and upper surfaces of the two spacers through etchback, and
wherein inner bottom surfaces of the two spacers are coplanar with the upper surface of the high-k layer after etching the inner side surfaces of the two spacers.

4. The manufacturing method of claim 1 , wherein each of the high-k layer, the first metal layer, and the WFC layer has a uniform thickness along the first direction,
the high-k layer is shorter than the first metal layer in the first direction, and
lengths of the first metal layer and the WFC layer are substantially equal to each other in the first direction.

5. The manufacturing method of claim 4 , wherein the high-k layer, the first metal layer, the WFC layer, and the second metal layer constitute a gate structure,
the gate structure extends on an upper surface of the fin shape and both side surfaces of the fin shape in the second direction,
the two spacers are respectively on both side surfaces of the gate structure in the first direction, and
inner side surfaces of the two spacers have respective steps adjacent to the first interface.

6. The manufacturing method of claim 1 , wherein the WFC layer comprises a WFC material, and a concentration of the WFC material on the first interface is uniform along the first direction.

7. The manufacturing method of claim 1 , wherein the high-k layer comprises a bottom portion extending on the lower surface of the first metal layer and protruding portions extending respectively on both side surfaces of the first metal layer in the first direction,
the WFC layer comprises a bottom portion extending on a lower surface of the second metal layer and protruding portions extending respectively on both side surfaces of the second metal layer in the first direction, and
the lower surface of the WFC layer is in contact with an upper surface of the first metal layer and upper surfaces of the protruding portions of the high-k layer.

8. The manufacturing method of claim 1 , wherein the WFC layer comprises aluminum (Al).

9. The manufacturing method of claim 1 , wherein lengths of the first metal layer and the WFC layer are substantially equal to each other in the first direction, and the lower surface of the WFC layer forms a second interface with an upper surface of the first metal layer, and
the second interface is longer than the first interface in the first direction.

10. The manufacturing method of claim 1 , wherein the high-k layer, the first metal layer, the WFC layer, and the second metal layer constitute a gate structure, and
the gate structure comprises side surfaces spaced apart from each other in the first direction, the two spacers are respectively on the side surfaces of the gate structures, and the inner side surfaces of the two spacers each have a step or a planar shape adjacent the first interface after etching the inner side surfaces of the two spacers.

11. A manufacturing method of a metal oxide field-effect transistor (MOSFET) device, the manufacturing method comprising:
forming an active area having a fin shape, protruding from a semiconductor substrate and extending in a first direction;
forming, on the semiconductor substrate, a dummy gate structure extending in a second direction that traverses the first direction and covering a portion of the active area;
forming two spacers respectively on side surfaces of the dummy gate structure, the side surfaces of the dummy gate structure being spaced apart from each other in the first direction;
removing the dummy gate structure between the two spacers;
conformally forming a high-k layer between the two spacers, the high-k layer comprising protruding portions extending respectively on inner side surfaces of the two spacers;
conformally forming a first metal layer on the high-k layer, the first metal layer comprising protruding portions extending respectively on the inner side surfaces of the two spacers;
removing the protruding portions of the high-k layer and the first metal layer;
conformally forming a work function control (WFC) layer on the high-k layer, the first metal layer, and the two spacers; and
conformally forming a second metal layer on the WFC layer,
wherein a lower surface of the WFC layer is longer than a first interface between a lower surface of the first metal layer and an upper surface of the high-k layer in the first direction.

12. The manufacturing method of claim 11 , wherein removing the protruding portions of the high-k layer comprises removing upper portions of the protruding portions of the high-k layer,
the high-k layer has a U-shape after removing the protruding portions of the high-k layer and covers the lower surface of the first metal layer and both side surfaces of the first metal layer, and the both side surfaces of the first metal layer are spaced apart from each other in the first direction, and
an upper surface of the first metal layer is on substantially the same plane as upper surfaces of the protruding portions of the high-k layer after removing the protruding portions of the high-k layer.

13. The manufacturing method of claim 12 , wherein the lower surface of the WFC layer forms a second interface with the upper surface of the first metal layer and the upper surfaces of the protruding portions of the high-k layer after removing the protruding portions of the high-k layer, and
the second interface is longer than the first interface in the first direction.

14. The manufacturing method of claim 11 , further comprising, after conformally forming the second metal layer, removing portions of the WFC layer and the second metal layer through chemical mechanical planarization (CMP) to expose upper surfaces of the two spacers,
wherein the WFC layer has a U-shape and covers a lower surface of the second metal layer and both side surfaces of the second metal layer, and the side surfaces of the second metal layer are spaced apart from each other in the first direction, and
an upper surfa

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yun Sangjun
• Kwon Uihui
• Kim Seongnam
• Ahn Hyoshin

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title