Semiconductor structure having a metal gate with side wall spacers

Patent metadata

Field	Value
Publication number	US-9397189-B2
Application number	US-201514698828-A
Country	US
Kind code	B2
Filing date	Apr 28, 2015
Priority date	Dec 2, 2009
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.

First claim

What is claimed is:

1. A method of forming a semiconductor structure having a metal gate, the method comprising the following steps:
providing a semiconductor substrate;
forming at least a gate structure on the semiconductor substrate, the gate structure comprising a gate dielectric layer and a gate sacrificial layer;
forming a spacer structure on a peripheral side wall of the gate structure;
forming an interlayer dielectric layer covering the gate structure and the spacer structure;
planarizing the interlayer dielectric layer to expose the gate sacrificial layer;
removing a portion of the gate sacrificial layer to an initial etching depth to form an opening and expose a portion of the spacer structure, wherein the initial etching depth is at least larger than half of a height of the gate sacrificial layer in the step of removing the portion of the sacrificial layer to the initial etching step;
after removing the portion of the gate sacrificial layer, removing a portion of the spacer structure exposed to the opening to broaden the opening;
removing the gate sacrificial layer completely; and
forming a gate conductive layer to fill the opening.

2. The method of claim 1 , wherein the step of broadening the opening comprises an etching process.

3. The method of claim 1 , wherein the step of broadening the opening comprises an ion bombardment process.

4. The method of claim 1 , wherein the spacer structure comprises a first spacer and a second spacer, wherein the first spacer is disposed on the peripheral side wall of the gate structure and the second spacer is disposed on the peripheral side wall of the first spacer.

5. The method of claim 4 , wherein the step of broadening the opening comprises partially removing the first spacer exposed to the opening till the initial etching depth.

6. The method of claim 4 , wherein the first spacer comprises at least an oxide layer and at least a silicon nitride layer.

7. The method of claim 6 , wherein the step of broadening the opening comprises removing the oxide layer and a part of the silicon nitride layer.

8. The method of claim 6 , wherein a thickness of each of the oxide layers and the silicon nitride layers is substantially between 1 nm and 5 nm.

9. The method of claim 1 , further comprising forming a work function layer before forming the conductive gate layer.

10. The method of claim 9 , wherein the work function layer comprises an N-type work function metal material or a P type work function metal material.

11. The method of claim 10 , wherein the N type work function metal material comprises titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), aluminum (Al), tantalum (Ta), titanium (Ti), titanium-aluminum (TiAI), titanium-aluminum-nitride (TiAlN) or hafnium (Hf).

12. The method of claim 10 , wherein the P-type work function metal material comprises titanium nitride (TiN), tungsten (W), tungsten nitride (WN), platinum (Pt), nickel (Ni), ruthenium (Ru), tantalum carbonitride (TaCN) or oxidized tantalum carbonitride (TaCNO).

13. The method of claim 9 , wherein the work function layer is a titanium nitride layer.

14. The method of claim 13 , wherein a thickness of the titanium nitride layer is substantially between 5 nm and 15 nm.

Assignees

• United Microelectronics Corp

Inventors

• Chen Yi-Wei
• Ho Nien-Ting
• Huang Chien-Chung
• Lin Chin-Fu

Classifications

• H10P50/20

  Dry etching; Plasma etching; Reactive-ion etching · CPC title

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10D64/01304

  characterised by the conductor · CPC title

• H10D64/665

  the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671) · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title