Group III-V semiconductor structures having crystalline regrowth layers and methods for forming such structures

Patent metadata

Field	Value
Publication number	US-11784248-B2
Application number	US-202218049368-A
Country	US
Kind code	B2
Filing date	Oct 25, 2022
Priority date	Oct 30, 2020
Publication date	Oct 10, 2023
Grant date	Oct 10, 2023

Abstract

A Group III-V semiconductor structure having a semiconductor device. The semiconductor device has a source and drain recess regions extending through a barrier layer and into a channel layer. A regrown, doped Group III-V ohmic contact layer is disposed on and in direct contact with the source and drain recess regions. A gate electrode is disposed in a gap in the regrown, doped Group III-V ohmic contact layer and on the barrier layer A dielectric structure is disposed over the ohmic contact layer and over the barrier layer and extending continuously from a region over the source recess region to one side of the stem portion and then extending continuously from an opposite side of the stem portion to a region over the drain recess region, a portion of the dielectric structure being in contact with the stem portion and the barrier layer.

First claim

What is claimed is:

1. A method comprising:
forming a semiconductor structure having a semiconductor device, the forming comprising:
forming a channel layer, the channel layer comprising a Group III-V material; forming a barrier layer on the channel layer, the barrier layer comprising a Group III-V material;
forming a vertically recessed source region and a vertically recessed drain region, the recessed source region and the recessed drain region passing through the barrier layer and into the channel layer;
growing a doped Group III-V layer in the vertically recessed source region and the vertically recessed drain region, the grown doped Group III-V layer comprising the same material as the channel layer, the doped Group III-V layer extending over a side of the vertically recessed source region and an opposing side of the vertically recessed drain region and extending continuously over the Group III-V barrier layer from the side of the vertically recessed source region to the opposing side of the vertically recessed drain region;
removing a portion of the grown doped Group III-V layer to expose a gate region over a surface of the barrier layer; and
forming a gate for the semiconductor device over the exposed gate region.

2. The method of claim 1 , wherein the semiconductor device is formed in a device region and wherein a portion of the grown doped Group III-V layer is outside of the device region.

3. The method of claim 1 , further comprising forming a dielectric structure over the grown doped Group III-V layer and over the gate.

4. The method of claim 1 , wherein the semiconductor device is formed in a device region, and
wherein a portion of the doped Group III-V layer on the barrier layer outside of the device region is single crystal material.

5. The method of claim 1 , wherein the semiconductor device is formed in a device region, and
wherein the grown doped Group III-V layer material in direct contact with a passivation layer disposed over Group III-V material of the barrier layer of the semiconductor device and the Group III-V material in a region outside of the device region is polycrystal while the Group III-V material in contact with the recessed source region and the recessed drain region is single crystal.

6. The method of claim 1 , wherein the doped Group III-V layer in contact with the recessed source region and the recessed drain region and the barrier layer is single crystal material.

7. The method of claim 1 , wherein the semiconductor device is formed in a device region, and
wherein the doped Group III-V layer outside of the device region is polycrystalline material.

8. The method of claim 1 , wherein the channel layer and the grown doped layer are single crystal material.

9. The method of claim 1 , wherein the channel layer and the doped layer comprise GaN.

10. The method of claim 1 , wherein the barrier layer comprises Al y Ga 1-x N here x is between 0 and 1.

11. The method of claim 1 , wherein the gate region is etched selectively through the doped Group III-V layer to stop on the Group III-V barrier layer.

12. The method of claim 1 , wherein the gate region is etched selectively through the doped Group III-V layer to stop on the barrier layer comprising Sc y Al 1-y N where y is between 0 and 0.5.

13. The method of claim 1 , wherein the semiconductor device is formed in a device region,
wherein a portion of the grown doped Group III-V layer in a region outside of the device region is monitored by measuring instrumentation during the growth of the grown doped Group III-V layer, and
wherein the doped Group III-V is grown as single crystal material in the region outside the device region.

14. The method of claim 13 , further comprising forming a dielectric structure over the grown doped Group III-V layer and over the gate, and
wherein the dielectric structure provides a passivation layer.

15. The method of claim 1 , wherein the semiconductor device has an extrinsic drain region and wherein the doped Group III-V layer extends into the extrinsic drain region of the semiconductor device.

16. A method comprising:
forming a semiconductor structure having a semiconductor device, disposed in a device region, the forming comprising:
forming a channel layer, the channel layer comprising a Group III-V material;
forming a barrier layer on the channel layer, the barrier layer comprising a Group III-V material;
forming a dielectric layer on the barrier layer, the dielectric layer exposing a source region and a drain region of the semiconductor device;
etching a vertically recessed source region and a vertically recessed drain regions in the exposed source region and the exposed drain region, the recessed source region and the recessed drain region passing through the barrier layer and into the channel layer;
growing a doped Group III-V layer in the vertically recessed source region and the vertically recessed drain region and over the dielectric layer, the grown doped Group III-V layer comprising the same material as the channel layer, the doped Group III-V layer extending over a side of the vertically recessed source region and an opposing side of the vertically recessed drain region and extending continuously over the dielectric layer from the side of the vertically recessed source region to the opposing side of the vertically recessed drain region and outside the device region;
removing a portion of the doped Group III-V layer deposited over the barrier layer;
forming an opening in the dielectric layer to expose a gate region over a surface of the barrier layer; and
forming a gate for the semiconductor device in the opening.

Assignees

• Raytheon Co

Inventors

• Laroche Jeffrey R
• Ip Kelly P
• Kazior Thomas E
• Chumbes Eduardo M

Classifications

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W74/134

  the encapsulations being in grooves in the semiconductor body · CPC title

• H10D64/0125

  characterised by the sectional shape, e.g. T or inverted T · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title