Method for forming gate structures for group III-V field effect transistors

Patent metadata

Field	Value
Publication number	US-10566428-B2
Application number	US-201815882250-A
Country	US
Kind code	B2
Filing date	Jan 29, 2018
Priority date	Jan 29, 2018
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

A method for forming a gate structure for a Field Effect Transistor includes providing a semiconductor. A dielectric layer is formed over the semiconductor with an opening therein over a selected portion of the semiconductor. A deposition process is used to selectively deposit a gate metal over the dielectric layer and into the opening, the gate metal being deposited being non-adherent to the dielectric layer by the gate metal deposition process.

First claim

What is claimed is:

1. A method for forming a gate electrical structure for a Field Effect Transistor, such gate electrode structure comprising: a lower gate electrode contract structure having a gate metal layer; and an upper electrode contact structure, the method comprising:
providing a semiconductor;
forming a dielectric layer over the semiconductor with an opening therein over a selected portion of the semiconductor;

using a deposition process to selectively deposit the gate metal layer of the lower gate electrode contact structure over the dielectric layer and into the opening, the gate metal layer being deposited being non-adherent to the dielectric layer by the gate metal layer deposition process; and
wherein the deposition process comprises depositing a gate metal oxide layer and subsequently chemically reducing the deposited gate metal oxide layer into the gate metal layer.

2. A method for forming a gate electrical structure for a Field Effect Transistor, such gate electrode structure comprising: a lower gate electrode contract structure having a gate metal layer; and an upper electrode contact structure, the method comprising:
providing a semiconductor;
forming a dielectric layer over the semiconductor with an opening therein over a selected portion of the semiconductor;

using a deposition process to selectively deposit the gate metal layer of the lower gate electrode contact structure over the dielectric layer and into the opening, the gate metal layer being deposited being non-adherent to the dielectric layer by the gate metal layer deposition process; and
wherein the deposition process comprises: depositing a gate metal oxide layer being non-adherent to the dielectric layer and adherent to the semiconductor; and subsequently chemically reacting the gate metal oxide layer to form the gate metal layer.

3. A method for forming a gate electrical structure for a Field Effect Transistor, such gate electrode structure comprising: a lower gate electrode contract structure having a gate metal layer; and an upper electrode contact structure, the method comprising:
providing a semiconductor;
forming a dielectric layer over the semiconductor with an opening therein over a selected portion of the semiconductor;

using a deposition process to selectively deposit the gate metal layer of the lower gate electrode contact structure over the dielectric layer and into the opening, the gate metal layer being deposited being non-adherent to the dielectric layer by the gate metal layer deposition process;
including forming an insulation layer over the semiconductor, the opening exposes the insulating layer, and wherein the deposition process comprises: depositing a gate metal oxide layer non-adherent to the dielectric layer by the gate metal layer deposition process and adherent to the insulating layer; and, chemically reducing the gate metal oxide layer to form the gate metal layer.

4. A method for forming a gate electrical structure for a Field Effect Transistor, such gate electrode structure comprising: a lower gate electrode contract structure having a gate metal layer; and an upper electrode contact structure, the method comprising:
providing a semiconductor;
forming a non-oxide dielectric layer over a surface of the semiconductor, the non-oxide dielectric layer having an opening therein disposed over a selected portion of the surface of the semiconductor;

subjecting the non-oxide dielectric layer and the exposed selected portion of the surface of the semiconductor to a gate metal deposition process wherein a gate metal being deposited is non-adherent to the non-oxide dielectric layer and is adherent to an oxide formed on the exposed selected portion of the surface of the semiconductor;
including forming an oxide insulation layer over the surface of the semiconductor, the opening exposing the oxide insulating layer, and wherein the gate metal is deposited is non-adherent to the non-oxide dielectric layer by the gate metal deposition process and adherent to the oxide insulating layer.

5. A method for forming a gate structure for a Field Effect Transistor, comprising:
providing a semiconductor;
forming a dielectric layer over the semiconductor with an opening therein over a selected portion of the semiconductor;

selectively depositing a gate metal oxide into the opening;
wherein the initial gate metal forming comprises Atomic Layer Deposition;
wherein the initial gate metal is a metal oxide; and
wherein the gate metal oxide layer is Nickel Oxide and annealing the Nickel Oxide in a reducing agent to convert the Nickel Oxide into Nickel to form the gate metal layer.

6. A method for forming a gate structure over a selected portion of a Group III-V semiconductor, comprising:
forming a dielectric layer over the semiconductor with an opening therein over a selected portion of the semiconductor;
forming Nickel Oxide on a surface exposed by the opening;
annealing the Nickel Oxide in a reducing agent to convert the Nickel Oxide into Nickel.

7. The method recited in claim 6 wherein the initial gate metal forming comprises Atomic Layer Deposition.

Assignees

• Raytheon Co

Inventors

• Laroche Jeffrey R

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0238

  comprising etching via holes through pads or through electrodes · CPC title

• H10D64/0125

  characterised by the sectional shape, e.g. T or inverted T · CPC title