Methods and structures for improved electrical contact between bonded integrated circuit interfaces

Patent metadata

Field	Value
Publication number	US-11784123-B2
Application number	US-202217677858-A
Country	US
Kind code	B2
Filing date	Feb 22, 2022
Priority date	Sep 26, 2019
Publication date	Oct 10, 2023
Grant date	Oct 10, 2023

Abstract

Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.

First claim

What is claimed is:

1. An integrated circuit (IC) device structure, comprising:
first metallization layers coupled with transistors of a first device layer;
second metallization layers coupled with transistors of a second device layer; and
a composite interconnect structure comprising:
a first metallization feature of one of the first metallization layers;
a second metallization feature of one of the second metallization layers; and
a metal between the first metallization feature and a bond interface with the second metallization feature.

2. The IC device structure of claim 1 , wherein
the first metallization feature is adjacent to a first dielectric material;
the second metallization feature is adjacent to a second dielectric material;
a plane of a bond interface between the first and second dielectric materials is offset from a plane of the bond interface with the second metallization feature toward the second device layer; and
a thickness of the metal is within the offset between the first and second bond interfaces.

3. The IC device structure of claim 2 , wherein the bond interface between the first and second dielectric materials intersects a sidewall of the metal.

4. The IC device structure of claim 2 , wherein the composite interconnect structure further comprises a first barrier material adjacent to a sidewall of the first dielectric material, and a second barrier material adjacent to a sidewall of the second dielectric material.

5. The IC device structure of claim 4 , wherein the metal is laterally confined to within the sidewalls of the first and second dielectric materials.

6. The IC device structure of claim 1 , wherein the metal comprises Cu.

7. The IC device structure of claim 6 , wherein the first metallization feature and the second metallization feature each comprise copper.

8. The IC device structure of claim 1 , wherein the metal has at least one of a different density, different crystallinity, or different impurity content than at least one of the first metallization feature or second metallization feature.

9. The IC device structure of claim 1 , wherein the metal has a thickness of at least 5 nm.

10. An integrated circuit (IC) device structure, comprising:
first metallization layers coupled with transistors of a first device layer;
second metallization layers coupled with transistors of a second device layer; and
a composite interconnect structure comprising:
a first metallization feature of one of the first metallization layers, wherein the first metallization feature is adjacent to a first dielectric material; and
a second metallization feature of one of the second metallization layers, wherein:
the second metallization feature is adjacent to a second dielectric material; and
the second metallization feature is joined to the first metallization feature at a first bond interface that is offset from a second bond interface between the dielectric materials toward one of the first or second device layers.

11. The IC device structure of claim 10 , wherein the first and second bond interfaces are offset by at least 5 nm.

12. The IC device structure of claim 10 , wherein at least one of the first metallization feature or the second metallization feature comprises copper.

13. The IC device structure of claim 10 , wherein at least one of the first metallization feature or the second metallization feature comprises a barrier layer between the copper and the adjacent dielectric materials, the barrier layer comprising at least one of Ta, Ti, or W.

14. The IC device structure of claim 10 , further comprising a metal between the first metallization feature and the bond interface with the second metallization feature, the metal having a thickness at least partially accounting for the offset between the first and second bond interfaces.

15. The IC device structure of claim 14 , wherein the metal has at least one of a different density, different crystallinity, or different impurity content than at least one of the first metallization feature or second metallization feature.

16. A method of fabricating an integrated circuit (IC) structure, the method comprising:
receiving a first workpiece with a first hybrid bonding interface comprising a first metallization feature adjacent to a first dielectric material;
receiving a second workpiece with a second hybrid bonding interface comprising a second metallization feature and a second dielectric material, wherein a top surface of the second metallization feature is proud of a surface of the adjacent dielectric material; and
joining the first workpiece to the second workpiece by bonding the first hybrid bonding interface to the second hybrid bonding interface.

17. The method of claim 16 , further comprising augmenting the second metallization feature with a selective deposition process until the top surface of the second metallization feature is proud of the surface of the adjacent dielectric material by no more than 100 nm.

18. The method of claim 17 , wherein the second metallization feature comprises copper and the selective deposition process comprises an autocatalytic Cu deposition process.

19. The method of claim 16 , further comprising selectively recessing a surface of the first or second dielectric material relative to a top surface of the second metallization feature with a dielectric etch process until the top surface of the second metallization feature is proud of the surface of the adjacent dielectric material by no more than 100 nm.

20. The method of claim 17 , further comprising:
forming the first hybrid bonding interface with a first chemical mechanical planarization (CMP) process that recesses a surface of the first metallization feature below a surface of the first dielectric material; and
forming the second hybrid bonding interface with a second CMP process that recesses a surface of the second metallization feature below a surface of the second dielectric material.

Assignees

• Intel Corp

Inventors

• Vreeland Richard
• Carver Colin
• Brezinski William
• Christenson Michael
• Kabir Nafees

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title