Methods and structures for improved electrical contact between bonded integrated circuit interfaces

Patent metadata

Field	Value
Publication number	US-11289421-B2
Application number	US-201916584666-A
Country	US
Kind code	B2
Filing date	Sep 26, 2019
Priority date	Sep 26, 2019
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.

First claim

What is claimed is:

1. An integrated circuit (IC) device structure, comprising:
first metallization layers interconnected with transistors of a first device layer;
second metallization layers interconnected with transistors of a second device layer; and
a composite interconnect structure comprising a first feature of one of the first metallization layers, a second feature of one of the second metallization layers, and an augmentation metal at a bond interface between the first and second features, wherein the augmentation metal comprises copper.

2. The IC device structure of claim 1 , wherein the first feature and the second feature each comprise copper.

3. The IC device structure of claim 2 , wherein the augmentation metal has at least one of a different density, different crystallinity, or different impurity content than at least one of the first or second features.

4. The IC device structure of claim 3 , wherein the augmentation metal has at least one of a higher density, or lower impurity content than at least one of the first or second features.

5. The IC device structure of claim 1 , wherein:
the first and second features have a lateral length of at least 1 μm; and
the augmentation metal has a thickness less than 100 nm.

6. The IC device structure of claim 1 , wherein:
the composite interconnect structure further comprises:
a first barrier material between a sidewall of the first feature and a first dielectric material; and
a second barrier material between a sidewall of the second feature and a second dielectric material; and

a bond interface between the first and second dielectric materials is offset from the augmentation metal toward one of the first or second device layers.

7. The IC device structure of claim 6 , wherein at least one of the first and second barrier materials comprise at least one of Ta, W, Ti, or N.

8. An integrated circuit (IC) device structure, comprising:
first metallization layers interconnected with transistors of a first device layer;
second metallization layers interconnected with transistors of a second device layer; and
a composite interconnect structure at a bond interface of one of the first metallization layers and one of the second metallization layers, wherein the composite interconnect structure comprises:
a first feature of one of the first metallization layers;
a first barrier material between a sidewall of the first feature and a first dielectric material;
a second feature of one of the second metallization layers, the second feature joined to the first feature at a first bond interface; and
a second barrier material between a sidewall of the second feature and a second dielectric material, wherein a second bond interface between the first and second dielectric materials is offset from the first bond interface toward one of the first or second device layers.

9. The IC device structure of claim 8 , wherein:
at least one of the first feature or the second feature comprises copper;
at least one of the first or second barrier materials comprises at least one of Ta, W, or Ti;
the first and second features each have a lateral length of at least 1 μm; and
the first and second bond interfaces are offset by less than 100 nm.

10. The IC device structure of claim 8 , wherein the composite interconnect structure further comprises an augmentation metal at the first bond interface, the augmentation metal having at least one of a different density, different crystallinity, or different impurity content than at least one of the first or second features.

11. The IC device structure of claim 10 , wherein the augmentation metal, the first feature, and the second feature all comprise copper, and wherein the augmentation metal has at least one of a higher density or lower impurity content than at least one of the first or second features.

12. A method of fabricating an integrated circuit (IC) structure, the method comprising:
forming a first hybrid bonding interface comprising a first metallization feature and a first dielectric material;
forming a second hybrid bonding interface comprising a second metallization feature and a second dielectric material;
selectively augmenting at least one of the first or second metallization features with an autocatalytic metal deposition process; and
bonding the first hybrid bonding interface to the second hybrid bonding interface.

13. The method of claim 12 , wherein:
forming the first hybrid bonding interface comprises a first chemical mechanical planarization process that recesses a surface of the first metallization feature below a surface of the first dielectric material;
forming a second hybrid bonding interface comprises a second chemical mechanical planarization process that recesses a surface of the second metallization feature below a surface of the second dielectric material; and
selectively augmenting at least one of the first or second metallization features comprises depositing a metal selectively onto at least one of the recessed surfaces of the first or second metallization features.

14. The method of claim 13 , wherein:
the first metallization feature comprises Cu; and
depositing the metal selectively further comprises depositing a metal comprising Cu upon the first metallization feature.

15. The method of claim 14 , wherein:
the first and second metallization features each have a lateral dimension of at least 1 μm;
the first and second metallization feature surfaces are recessed below the dielectric surfaces by less than 50 nm; and
selectively augmenting at least one of the first or second metallization features comprises depositing a metal to a thickness of less than 100 nm.

16. The method of claim 12 further comprising selectively recessing a surface of at least one of the first or second dielectric materials relative to a surface of the first or second metallization features with a dielectric etch process prior to the bonding.

17. A method of fabricating an integrated circuit (IC) structure, the method comprising:
forming a first hybrid bonding interface comprising a first metallization feature and a first dielectric material;
forming a second hybrid bonding interface comprising a second metallization feature and a second dielectric material;
selectively recessing a surface of at least one of the first or second dielectric materials relative to a surface of the first or second metallization features with a dielectric etch process; and
bonding the first hybrid bonding interface to the second hybrid bonding interface.

18. The method of claim 17 , wherein:
the first and second metallization features each have a lateral dimension of at least 1 μm;
forming the first hybrid bonding interface comprises a first chemical mechanical planarization (CMP) process that recesses a surface of the first metallization feature below a surface of the first dielectric material;
forming the second hybrid bonding interface comprises a second CMP process that recesses a surface of the second metallization feature below a surface of the second dielectric material; and
selectively recessing the surface of at least one of the first or second dielectric materials further comprises removing less than 100 nm from the first dielectric material.

19. The method of claim 18 , wherein:
the first metallization feature comprises Cu; and
selectively recessing the surface of at least one of the first or second dielectric materials further comprises etching the first dielectric material with a fluorine-based plasma.

Assignees

• Intel Corp

Inventors

• Vreeland Richard
• Carver Colin
• Brezinski William
• Christenson Michael
• Kabir Nafees

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title