Translation support for a virtual cache

Patent metadata

Field	Value
Publication number	US-11775445-B2
Application number	US-202017069290-A
Country	US
Kind code	B2
Filing date	Oct 13, 2020
Priority date	Jun 16, 2017
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

First claim

What is claimed is:

1. A method of operating a primary processor cache for a processor with virtual memory support and multiple threads, wherein a logically indexed and logically tagged cache directory is used, and wherein an entry in the directory contains an absolute memory address in addition to a corresponding logical memory address, each entry includes a valid bit for each thread that accesses each entry, comprising:
creating a new entry for the cache line in the primary cache in response to the cache line being in a secondary cache, and not in the primary cache;
determining by a second thread that an entry for the cache line is present in the primary cache;
in response to determining that the entry for the cache line is present in the primary cache, determining that the cache line is not valid for the second thread;
executing a lookup to determine an address for the cache line in the primary cache;
determining that the address for the cache line and the entry are the same cache line;
in response to determining that the address and the entry are the same, setting the valid bit associated with the second thread to valid, and not invalidating the valid bit associated with other threads in the cache entry that have a valid bit in the cache entry, and not creating an additional cache entry, wherein the valid bit is independent of other valid bits in the cache entry.

2. The method of claim 1 wherein the secondary cache is an L2 cache.

3. The method of claim 1 wherein the secondary cache is an L3 cache.

4. The method of claim 1 wherein creating the new entry overwrites a previous entry in the primary cache.

5. The method of claim 1 wherein creating the new entry copies the cache line from the secondary cache to the primary cache.

6. The method of claim 5 wherein creating sets the valid bit associated with the first thread in the cache line to on.

7. The method of claim 6 wherein creating invalidates the valid bit associated with any other threads in the cache line.

8. The method of claim 1 further comprising:
determining that a cache line is not in the primary cache based on a thread shared entry in the directory, and wherein the first thread has a thread private entry in the cache directory.

9. A computer program product having computer executable instructions for operating a processor with virtual memory support and multiple threads wherein a logically indexed and logically tagged cache directory is used, and wherein an entry in the directory contains an absolute memory address in addition to a corresponding logical memory address, each entry includes a valid bit for each thread that accesses each entry, that when executed cause at least one computer to execute a method comprising:
creating a new entry for a cache line in the primary cache in response to the cache line being in a secondary cache, and not in the primary cache;
determining by a second thread that an entry for the cache line is present in the primary cache;
in response to determining that the entry for the cache line is present in the primary cache, determining that the cache line is not valid for the second thread;
executing a lookup to determine an address for the cache line in the primary cache;
determining that the address for the cache line and the entry are the same cache line;
in response to determining that the address and the entry are the same, setting the valid bit associated with the second thread to valid, and not invalidating the valid bit associated with other threads in the cache entry, and not creating an additional cache entry, wherein the valid bit is independent of other valid bits in the cache entry.

10. The computer program product of claim 9 wherein the secondary cache is an L2 cache.

11. The computer program product of claim 9 wherein creating the new entry overwrites a previous entry in the primary cache.

12. The computer program product of claim 9 wherein creating the new entry copies the cache line from the secondary cache to the primary cache.

13. The computer program product of claim 12 wherein creating sets the valid bit associated with the first thread in the cache line to on.

14. The computer program product of claim 13 wherein creating invalidates the valid bit associated with any other threads in the cache line.

15. The computer program product of claim 9 further comprising:
determining, by the first thread, that the cache line is not present in the primary cache.

16. The computer program product of claim 15 wherein determining that the cache line is not in the primary cache, determines based on a thread shared entry in the directory, and wherein the first thread has a thread private entry in the cache directory.

17. The computer program product of claim 9 further comprising: determining that the cache line is in the secondary cache.

Assignees

• IBM

Inventors

• Helms Markus
• Jacobi Christian
• Mayer Ulrich
• Recktenwald Martin
• Reichart Johannes C
• Saporito Anthony
• Tsai Aaron

Classifications

• G06F12/1063 Primary

  the data cache being concurrently virtually addressed · CPC title

• G06F12/0808

  with cache invalidating means (G06F12/0815 takes precedence) · CPC title

• G06F12/0817

  using directory methods · CPC title

• G06F12/0842 Primary

  for multiprocessing or multitasking · CPC title

• G06F12/0864

  using pseudo-associative means, e.g. set-associative or hashing · CPC title