Cache Accessed Using Virtual Addresses

Patent metadata

Field	Value
Publication number	US-2016188486-A1
Application number	US-201514867926-A
Country	US
Kind code	A1
Filing date	Sep 28, 2015
Priority date	Dec 26, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

A computer architecture provides a memory cache that is accessed not by physical addresses but by virtual addresses directly from running processes. Ambiguities that can result from multiple virtual addresses mapping to a single physical address are handled by dynamically tracking synonyms and connecting a limited number of virtual synonyms mapping to the same physical address to a single key virtual address that is used exclusively for cache access.

First claim

What we claim is:

1 . An electronic processor architecture for use with a memory having storage at physical addresses comprising:
a processor; a memory cache; a cache control circuit caching memory data of a physical address by virtual address; a translation circuit for translating between a virtual address from the processor and a physical address; and a synonym tracking circuit receiving a given virtual address from the processor for access to the cache and (1) determining if the given virtual address is a synonym with an other virtual address mapping to a same given physical memory address of data in the cache; and (2) when the given virtual memory address is a synonym, accessing the memory cache using the other virtual address as an accessing address for the memory cache.

2 . The electronic processor of claim I wherein the memory cache holds data of a physical address accessible only by a virtual address.

3 . The electronic processor of claim I wherein each other virtual address is a key virtual address being a synonym of multiple virtual addresses but a synonym of no other key virtual address.

4 . The electronic processor of claim I wherein when the given virtual address is not a synonym with another virtual address, the synonym tracking accesses the memory cache using the given virtual memory address as the accessing address for the memory cache.

5 . The electronic processor of claim I wherein the synonym tracking circuit includes a first table of virtual addresses linked as synonyms to determine if a given virtual addresses is a synonym.

6 . The electronic processor of claim 5 wherein the first table of virtual addresses linked as synonyms provides a virtual address linked to the given virtual address as the other virtual address when the given virtual address is in the first table.

7 . The electronic processor of claim 6 wherein the first table further includes a set of memory access permissions associated with a linked sets of virtual addresses and wherein when the other virtual address is used as the accessing instruction, accesses to the cache memory are controlled by the permissions of the first table.

8 . The electronic processor of claim 5 wherein the synonym tracking circuit includes a compressed signature of at least some of the virtual addresses in the first table, the compressed signature indicating whether the given virtual address is likely in the first table and wherein the synonym tracking circuit first checks the compressed signature and checks the first table only if a compressed signature indicates that the given virtual address is likely in the first table.

9 . The electronic processor of claim 5 wherein the synonym tracking circuit responds to a cache miss of the memory cache by determining a physical address associated with the given virtual address and applying the determined physical address to a second table linking a physical addresses and virtual addresses, and when a determined physical address links to a virtual address in the second table, using the virtual address of the second table as an accessing address for the memory cache.

10 . The electronic, processor of claim 9 wherein the second table further associates linked physical addresses and virtual, addresses with memory access permissions which control the access of memory when using a linked physical and virtual address.

11 . The electronic processor of claim 9 wherein a line of the cache memory holds an index to a corresponding entry of the second table linked to a corresponding virtual address and wherein the synonym tracking circuit receives the index to identify an entry in the second table for updating when a line of a cache memory is evicted or invalidated.

12 . The electronic processor of claim 9 wherein only a single key virtual address in the second table links to a given physical address.

13 . The electronic processor of claim 12 wherein the processor is an out of order processor using a load queue and a store queue and wherein a data in the load queue and the store queue store is linked to a key virtual address.

14 . The electronic processor of claim 9 wherein the synonym tracking circuit uses a translation lookaside buffer and a page table to convert a given virtual address to a physical address.

15 . The electronic processor of claim 9 wherein second table may further identify to each physical address of the second table subsets of data of the physical address in the cache memory and the cache control circuit may use the second table to identify portions of physical addresses of the second table enrolled in the cache memory.

16 . The electronic processor of claim 9 wherein the second table provides a counter associated with a physical address indicating a number of subsets of that physical address enrolled in the cache.

17 . A method of caching data in an electronic processor computer system of a type including at least one processor together with a memory cache and a cache control circuit caching memory data of physical addresses by virtual addresses, the processor further including a translation circuit for translating between a virtual address from the processor and a physical address; and a synonym tracking circuit receiving a given virtual address from the processor to determine if the given virtual address is a synonym with an other virtual address mapping to a same given physical memory address of data in the cache; and when the given virtual memory address is a synonym, accessing the memory cache using the other virtual address as an accessing address for the memory cache, the method comprising:
(1) saving data in the memory cache using a virtual address wherein the cache holds at least a portion of the virtual address; and (2) accessing data from the memory cache using a given virtual address by first determining if the given virtual address has a designated synonym virtual address for accessing the memory cache and if so using the designated synonym virtual, address for accessing the memory cache.

18 . The method of claim 17 wherein the step of saving data in the memory cache using a virtual address allows access to the saved data only with a virtual address.

19 . The method of claim 17 wherein the designated virtual address is a synonym of multiple virtual addresses but a synonym of no other key virtual address.

Assignees

• Wisconsin Alumni Res Found

Inventors

• Sohi Gurindar S
• Yoon Hongil

Classifications

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0664

  at device level, e.g. emulation of a storage device or system · CPC title

• G06F2212/50

  Control mechanisms for virtual memory, cache or TLB · CPC title

• G06F3/0638

  Organizing or formatting or addressing of data · CPC title