Virtualizing input/output interrupts
US-2015356038-A1 · Dec 10, 2015 · US
Effective address cache memory, processor and effective address caching method
US8949572B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8949572-B2 |
| Application number | US-58073209-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 16, 2009 |
| Priority date | Oct 20, 2008 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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Abstract
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An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.
First claim
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What is claimed is: 1. An effective address cache memory, comprising: a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process with a plurality of low-order bits including a least significant bit in the effective page tag as a first index, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain ca…
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- G06F12/1054Primary
Physics · mapped topic
Physics · mapped topic
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- What does patent US8949572B2 cover?
- An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset…
- Who is the assignee on this patent?
- Kurosawa Yasuhiko, Iwasa Shigeaki, Maeda Seiji, and 4 more
- What technology area does this patent fall under?
- Primary CPC classification G06F12/1054. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).