Averting lock contention associated with core-based hardware threading in a split core environment

Patent metadata

Field	Value
Publication number	US-10102037-B2
Application number	US-201615199275-A
Country	US
Kind code	B2
Filing date	Jun 30, 2016
Priority date	Jun 30, 2016
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

Techniques are disclosed for managing lock contention in a multithreaded processing system. In one embodiment, a method includes tracking an amount of time that a lock on a first thread prevents a second thread from execution. The method also includes, if the amount of time is greater than a first threshold, storing the amount of time and an address associated with the lock. The method includes dispatching a third thread that utilizes the address associated with the lock. The method also includes increasing the hardware priority of the third thread during a lock operation.

First claim

What is claimed is:

1. A method for managing lock contention in a processor, comprising:
executing a first software thread comprising a first operation which executes a first lock at an address of the first lock;
receiving, during the execution of the first lock, a request from a second software thread comprising a load request to the address of the first lock, wherein the first lock prevents the second software thread from executing;
tracking an amount of time that the first lock during the execution of the first software thread prevents the second software thread from executing;
if the amount of time is greater than a threshold, storing, in a lock history table, the amount of time and the address of the first lock;
dispatching, after the first lock is cleared, a third software thread, wherein the third software thread comprises a second operation that attempts to execute a second lock at an address;
determining that the address of the second lock matches the address of the first lock stored in the lock history table;
executing the third software thread and the second lock at the address of the second lock; and
increasing the hardware priority of the third software thread during the second lock, wherein the increased hardware priority reduces the duration of the second lock.

2. The method of claim 1 , further comprising:
reducing the hardware priority of the third software thread when the second lock is cleared.

3. The method of claim 1 , wherein the second software thread enters a lower hardware thread priority mode when prevented from execution.

4. The method of claim 1 , wherein each new entry in the lock history table dispatches an older entry.

5. The method of claim 4 , wherein the lock history table is reset at a beginning of a dispatch cycle for the processor.

6. The method of claim 1 , wherein tracking the amount of time comprises utilizing one or more instruction hint bits to denote a beginning and an end of the first lock.

7. A computer program product for managing lock contention, the computer program product comprising a non-transitory computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by a processor to cause the processor to:
execute a first software thread comprising a first operation which executes a first lock at an address of the first lock;
receive, during the execution of the first lock, a request from a second software thread comprising a load request to the address of the first lock, wherein the first lock prevents the second software thread from executing;
track an amount of time that the first lock during the execution of the first software thread prevents the second software thread from executing;
if the amount of time is greater than a threshold, store, in a lock history table, the amount of time and the address of the first lock;
dispatch, after the first lock is cleared, a third software thread, wherein the third software thread comprises a second operation that attempts to execute a second lock at an address;
determine that the address of the second lock matches the address of the first lock stored in the lock history table;
execute the third software thread and the second lock at the address of the second lock; and
increase the hardware priority of the third software thread during the second lock, wherein the increased hardware priority reduces the duration of the second lock.

8. The computer program product of claim 7 , wherein the computer-readable program code further causes the processor to:
reduce the hardware priority of the third software thread when the second lock is cleared.

9. The computer program product of claim 7 , wherein the second software thread enters a lower hardware thread priority mode when prevented from execution.

10. The computer program product of claim 7 , wherein each new entry in the lock history table dispatches an older entry.

11. The computer program product of claim 10 , wherein the lock history table is reset at a beginning of a dispatch cycle for the processor.

12. The computer program product of claim 7 , wherein tracking the amount of time comprises utilizing one or more instruction hint bits to denote a beginning and an end of the first lock.

13. A system, comprising:
a processor; and
a memory storing a program, which, when executed on the processor, performs an operation for managing lock contention, the operation comprising:
executing a first software thread comprising a first operation which executes a first lock at an address of the first lock;
receiving, during the execution of the first lock, a request from a second software thread comprising a load request to the address of the first lock, wherein the first lock prevents the second software thread from executing;
tracking an amount of time that the first lock during the execution of the first software thread prevents the second software thread from executing;
if the amount of time is greater than a threshold, storing, in a lock history table, the amount of time and the address of the first lock;
dispatching, after the first lock is cleared, a third software thread, wherein the third software thread comprises a second operation that attempts to execute a second lock at an address;
determining that the address of the second lock matches the address of the first lock stored in the lock history table;
executing the third software thread and the second lock at the address of the second lock; and
increasing the hardware priority of the third software thread during the second lock, wherein the increased hardware priority reduces the duration of the second lock.

14. The system of claim 13 , the operation further comprising:
reducing the hardware priority of the third software thread when the second lock is cleared.

15. The system of claim 13 , wherein the second software thread enters a lower hardware thread priority mode when prevented from execution.

16. The system of claim 13 , wherein each new entry in the lock history table dispatches an older entry.

17. The system of claim 16 , wherein the lock history table is reset at a beginning of a dispatch cycle for the processor.

Assignees

• IBM

Inventors

• Accapadi Mathew
• Davidson Ii Grover C
• Michel Dirk
• Olszewski Bret R

Classifications

• G06F9/5038 Primary

  considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration (scheduling strategies G06F9/4881 and subgroups) · CPC title

• G06F9/52

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

• G06F9/524 Primary

  Deadlock detection or avoidance · CPC title