Memory device and method of manufacturing memory device

Patent metadata

Field	Value
Publication number	US-11765916-B2
Application number	US-202117348839-A
Country	US
Kind code	B2
Filing date	Jun 16, 2021
Priority date	Jun 17, 2020
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

First claim

What is claimed is:

1. A memory device comprising:
a first conductive layer, at least a single second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer being stacked above a substrate in this order in a first direction;
a first insulating layer splitting each of the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer into a first portion and a second portion aligned in a second direction orthogonal to the first direction;
a second insulating layer splitting the first portion of the second conductive layer into a first sub portion and a second sub portion aligned in the second direction;
a third insulating layer splitting the first portion of the fifth conductive layer into a first sub portion and a second sub portion aligned in the second direction;
a first structure extending in the first direction in the first portion of the first conductive layer and the first sub portion of the second conductive layer, and being in contact with a lower surface of the first portion of the third conductive layer;
a second structure extending in the first direction in the first portion of the first conductive layer and the second sub portion of the second conductive layer and being in contact with a lower surface of the first portion of the third conductive layer;
a third structure extending in the first direction in the first portion of the fourth conductive layer and the first sub portion of the fifth conductive layer and being in contact with an upper surface of the first portion of the third conductive layer; and
a fourth structure extending in the first direction in the first portion of the fourth conductive layer and the second sub portion of the fifth conductive layer and being in contact with an upper surface of the first portion of the third conductive layer,
wherein:
each of the first structure and the second structure includes:
a first resistance change film extending in the first direction in the first conductive layer;
a first semiconductor film extending in the first direction in the first conductive layer and the second conductive layer and being in contact with the first resistance change film in the first direction; and
a first insulating film provided between the first conductive layer and the first semiconductor film and between the second conductive layer and the first semiconductor film; and

each of the third structure and the fourth structure includes:
a second resistance change film extending in the first direction in the fourth conductive layer;
a second semiconductor film extending in the first direction in the fourth conductive layer and the fifth conductive layer and being in contact with the second resistance change film in the first direction; and
a second insulating film provided between the fourth conductive layer and the second semiconductor film and between the fifth conductive layer and the second semiconductor film.

2. The memory device according to claim 1 , wherein the first resistance change film in each of the first structure and the second structure extends in the first direction in the first conductive layer and the second conductive layer.

3. The memory device according to claim 2 , wherein a thickness of the second conductive layer in the first direction is greater than a thickness of the fifth conductive layer in the first direction.

4. The memory device according to claim 2 , wherein a number of the second conductive layers stacked in the first direction is greater than a number of the fifth conductive layers stacked in the first direction.

5. The memory device according to claim 1 , wherein a lower end of each of the first structure and the second structure is in contact with the substrate.

6. The memory device according to claim 1 , further comprising a sixth conductive layer provided between the substrate and the first conductive layer and being in contact with a lower end of each of the first structure and the second structure.

7. The memory device according to claim 6 , wherein a thickness of the sixth conductive layer in the first direction is greater in an area where the sixth conductive layer is in contact with the first structure and the second structure than in an area between the first portion and the second portion of the first conductive layer.

8. A memory device comprising:
a first conductive layer, at least a single second conductive layer, a third conductive layer, and a fourth conductive layer being stacked in this order in a first direction;
a first insulating layer splitting the second conductive layer into a first portion and a second portion in a second direction orthogonal to the first direction;
a first structure extending in the first direction through the first conductive layer, the first portion of the second conductive layer, the third conductive layer, and the fourth conductive layer; and
a second structure extending in the first direction through the first conductive layer, the second portion of the second conductive layer, the third conductive layer, and the fourth conductive layer,
wherein:
the first structure includes a first resistance change film and a first semiconductor film being in contact with the first resistance change film in the first direction,
the second structure includes a second resistance change film and a second semiconductor film being in contact with the second resistance change film in the first direction,
the first semiconductor film is located between the first resistance change film and the third conductive layer,
the second semiconductor film is located between the second resistance change film and the third conductive layer, and
the first semiconductor film, the second semiconductor film, and the third conductive layer are connected to each other.

9. The memory device according to claim 8 , further comprising a fifth conductive layer provided on a side of the fourth conductive layer in the first direction,
wherein:
the first resistance change film extends in the first direction through the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer,
the first semiconductor film extends in the first direction through the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer,
the second resistance change film extends in the first direction through the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer, and
the second semiconductor film extends in the first direction through the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer.

10. The memory device according to claim 8 , further comprising:
a fifth conductive layer provided on a side of the fourth conductive layer in the first direction; and
a second insulating layer splitting the fifth conductive layer into a third portion and a fourth portion aligned in the second direction,
wherein:
the first structure extends in the first direction through the third portion of the fifth conductive layer, and
the second structure extends in the first direction through the fourth portion of the fifth conductive layer.

11. The memory device according to claim 8 , wherein:
the first structure further comprises a first insulating film provided between the first conductive layer and the first semiconductor film, between the second conductive layer and the first semiconductor film, and between the fourth conduct

Assignees

• Kioxia Corp

Inventors

• Iizuka Takahiko
• Takashima Daisaburo
• Ogiwara Ryu
• Funatsuki Rieko
• Kamata Yoshiki
• Morota Misako
• Asao Yoshiaki
• Nomura Yukihiro

Classifications

• H10N70/8265

  on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices · CPC title

• G11C13/003 Primary

  Cell access · CPC title

• H10B63/845 Primary

  the switching components being connected to a common vertical conductor · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C2213/75

  Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor · CPC title