Memory device

Patent metadata

Field	Value
Publication number	US-10930847-B2
Application number	US-201916562352-A
Country	US
Kind code	B2
Filing date	Sep 5, 2019
Priority date	Mar 20, 2019
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

A memory device of an embodiment includes: a first conductive layer; a second conductive layer; a first region provided between the first conductive layer and the second conductive layer, being in contact with the first conductive layer and the second conductive layer, and including a first metal oxide, the first metal oxide corresponding to at least one selected from a group consisting of tantalum oxide, lanthanum oxide, and hafnium oxide; and a first layer provided between the first conductive layer and the second conductive layer and including a second metal oxide different from the first metal oxide.

First claim

What is claimed is:

1. A memory device comprising:
a first conductive layer;
a second conductive layer;
a first region provided between the first conductive layer and the second conductive layer, the first region being in contact with the first conductive layer and the second conductive layer, the first region including a first metal oxide, and the first metal oxide being at least one metal oxide selected from a group consisting of tantalum oxide, lanthanum oxide, and hafnium oxide;
a first layer provided between the first conductive layer and the second conductive layer, the first layer including a second metal oxide different from the first metal oxide; and
a second region provided at least one of a position between the first conductive layer and the first layer and a position between the second conductive layer and the first layer, the second region including the first metal oxide, and the second region being in contact with the first region.

2. The memory device according to claim 1 , wherein the first region has a cross-sectional area in a plane perpendicular to a direction from the first conductive layer to the second conductive layer, the cross-sectional area being equal to or more than 0.33 times and equal to or less than one time of a cross-sectional area of the first layer in the plane.

3. The memory device according to claim 1 , further comprising a second layer provided at one of a position between the first conductive layer and the first layer and a position between the second conductive layer and the first layer and including a third metal oxide different from both of the first metal oxide and the second metal oxide.

4. The memory device according to claim 3 , wherein the first layer and the second layer are in contact with each other.

5. The memory device according to claim 1 , wherein the second metal oxide is at least one metal oxide selected from a group consisting of titanium oxide, aluminum oxide, tantalum oxide, and hafnium oxide.

6. The memory device comprising:
a first conductive layer extending in a first direction;
a second conductive layer extending in a second direction intersecting the first direction;
a first region provided between the first conductive layer and the second conductive layer, the first region being in contact with the first conductive layer and the second conductive layer, and the first region including a first metal oxide;
a resistive change element provided between the first conductive layer and the second conductive layer; and
a second region provided at one of a position between the first conductive layer and the resistive change element and a position between the second conductive layer and the resistive change element, the second region including the first metal oxide, and the second region being in contact with the first region.

7. The memory device according to claim 6 , wherein the first region has a width in the first direction, the width being greater than a width of the second conductive layer in the first direction.

8. The memory device according to claim 6 , wherein the first region has a cross-sectional area in a plane perpendicular to a direction from the first conductive layer to the second conductive layer, the cross-sectional area being equal to or more than 0.33 times and equal to or less than one time of a cross-sectional area of the resistive change element in the plane.

9. The memory device according to claim 6 , wherein the first metal oxide is at least one metal oxide selected from a group consisting of tantalum oxide, lanthanum oxide, and hafnium oxide.

10. The memory device according to claim 6 , wherein the resistive change element includes a first layer including a second metal oxide different from the first metal oxide.

11. The memory device according to claim 10 , wherein the second metal oxide is at least one metal oxide selected from a group consisting of titanium oxide, aluminum oxide, tantalum oxide, and hafnium oxide.

12. The memory device according to claim 10 , wherein the resistive change element includes a second layer provided at one of a position between the first conductive layer and the first layer and a position between the second conductive layer and the first layer, and the resistive change element including a third metal oxide different from both of the first metal oxide and the second metal oxide.

13. A memory device comprising:
a first conductive layer;
a second conductive layer;
a first region provided between the first conductive layer and the second conductive layer, the first region being in contact with the first conductive layer and the second conductive layer; and
a resistive change element provided between the first conductive layer and the second conductive layer, the resistive change element being changed from a high resistance state to a low resistance state by applying a predetermined write voltage between the first conductive layer and the second conductive layer,
wherein, when a predetermined read voltage is applied between the first conductive layer and the second conductive layer, the first region has a resistance lower than a resistance of the resistive change element in the high resistance state, and the first region has a resistance higher than a resistance of the resistive change element in the low resistance state.

14. The memory device according to claim 13 ,
wherein, when a voltage of half the predetermined write voltage is applied between the first conductive layer and the second conductive layer, the first region has a resistance higher than a resistance of the resistive change element in the high resistance state, and
when a voltage of half the predetermined read voltage is applied between the first conductive layer and the second conductive layer, the first region has a resistance higher than a resistance of the resistive change element in the high resistance state.

Assignees

• Toshiba Memory Corp

Inventors

• Yamaguchi Marina
• Saitoh Masumi
• Sakuma Kiwamu

Classifications

• G11C2213/71

  Three dimensional array · CPC title

• G11C13/0028

  Word-line or row circuits · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C2013/0078

  Write using current through the cell · CPC title

• G11C2013/0045

  Read using current through the cell · CPC title