Storage device

Patent metadata

Field	Value
Publication number	US-10651239-B2
Application number	US-201916290651-A
Country	US
Kind code	B2
Filing date	Mar 1, 2019
Priority date	Sep 18, 2018
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

A storage device includes: a first conductive layer; a second conductive layer; and a resistance-variable layer disposed between the first conductive layer and the second conductive layer, and including a first chalcogenide containing a first element which is either silicon or germanium. An insulating layer is disposed in a second direction perpendicular to a first direction from the first conductive layer to the second conductive layer with respect to the resistance-variable layer. A first region is disposed between the resistance-variable layer and the insulating layer, and has a third concentration of the first element higher than both a first concentration of the first element in the resistance-variable layer and a second concentration of the first element in the insulating layer.

First claim

What is claimed is:

1. A storage device comprising:
a first conductive layer;
a second conductive layer;
a resistance-variable layer disposed between the first conductive layer and the second conductive layer, and including a first chalcogenide containing a first element which is either silicon or germanium;
an insulating layer disposed in a second direction perpendicular to a first direction, the first direction being from the first conductive layer to the second conductive layer with respect to the resistance-variable layer; and
a first region disposed between the resistance-variable layer and the insulating layer, and having a third concentration of the first element higher than both a first concentration of the first element in the resistance-variable layer and a second concentration of the first element in the insulating layer.

2. The storage device according to claim 1 further comprising:
an intermediate layer disposed between the first conductive layer and the resistance-variable layer, and including a second chalcogenide containing a second element which is either silicon or germanium; and
a second region disposed between the intermediate layer and the insulating layer, and having a sixth concentration of the second element higher than both a fourth concentration of the second element in the intermediate layer and a fifth concentration of the second element in the insulating layer.

3. The storage device according to claim 2 , wherein
the first element and the second element are different from each other.

4. The storage device according to claim 2 , wherein
the first chalcogenide includes germanium, antimony, and tellurium, and
the second chalcogenide includes silicon and tellurium.

5. The storage device according to claim 3 , wherein
the first chalcogenide includes germanium, antimony, and tellurium, and
the second chalcogenide includes silicon and tellurium.

6. The storage device according to claim 1 , wherein
the insulating layer is silicon oxide, silicon nitride, or silicon oxynitride.

7. The storage device according to claim 2 , wherein
the insulating layer is silicon oxide, silicon nitride, or silicon oxynitride.

8. The storage device according to claim 1 , wherein
a width in the second direction of the first region is less than 0.5 nm.

9. The storage device according to claim 2 , wherein
a width in the second direction of the first region is less than 0.5 nm.

10. The storage device according to claim 1 , wherein the first region is disposed on opposing sides of the resistance-variable layer.

11. A storage device array, comprising:
a plurality of storage devices according to claim 1 arranged in an array.

12. The storage device array of claim 11 , further comprising:
a plurality of word lines connected respectively to the first conductive layers of the storage devices.

13. The storage device array of claim 11 , further comprising:
a plurality of bit lines connected respectively to the second conductive layers of the storage devices.

14. The storage device array of claim 11 , wherein the storage devices are arranged three-dimensionally.

Assignees

• Toshiba Memory Corp

Inventors

• Yamamoto Kazuhiko

Classifications

• G11C2213/77

  Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C13/0004 Primary

  comprising amorphous/crystalline phase transition cells · CPC title

• H01L27/2436 Primary

  Electricity · mapped topic

• H01L27/2409

  Electricity · mapped topic