Three-dimensional memory device without gate line slits and method for forming the same

Patent metadata

Field	Value
Publication number	US-11765897-B2
Application number	US-202017100874-A
Country	US
Kind code	B2
Filing date	Nov 21, 2020
Priority date	Jun 17, 2019
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes forming a bottom select structure extending along a vertical direction through a bottom conductor layer over a substrate and along a horizontal direction to divide the bottom conductor layer into a pair of bottom select conductor layers, forming a plurality of conductor layers and a plurality of insulating layers interleaved on the pair of bottom select conductor layers and the bottom select structure, and forming a plurality of channel structures extending along the vertical direction through the pair of bottom select conductor layers, the plurality of conductor layers, and the plurality of insulating layers and into the substrate. The method may further include forming a first top select structure extending along the vertical direction through a top conductor layer of the plurality of conductor layers and along the horizontal direction to divide the top conductor layer into a pair of top select conductor layers. The first top select structure and the bottom select structure may be aligned along the vertical direction and may divide a plurality of memory cells formed by the plurality of conductor layers and the plurality of channel structures into a pair of memory blocks.

First claim

What is claimed is:

1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a bottom select structure extending along a vertical direction through a bottom conductor layer over a substrate and along a horizontal direction to divide the bottom conductor layer into a pair of bottom select conductor layers;
forming a plurality of conductor layers and a plurality of insulating layers interleaved on the pair of bottom select conductor layers and the bottom select structure;
forming a plurality of channel structures extending along the vertical direction through the pair of bottom select conductor layers, the plurality of conductor layers, and the plurality of insulating layers and into the substrate; and
forming a first top select structure extending along the vertical direction through a top conductor layer of the plurality of conductor layers and along the horizontal direction to divide the top conductor layer into a pair of top select conductor layers, the first top select structure and the bottom select structure being aligned along the vertical direction and dividing a plurality of memory cells formed by the plurality of conductor layers and the plurality of channel structures into a pair of memory blocks.

2. The method of claim 1 , wherein forming a bottom conductor layer comprises forming a buffer oxide layer over the substrate and forming a bottom conductor material layer on the buffer oxide layer.

3. The method of claim 2 , wherein forming the bottom select structure comprises:
patterning the bottom conductor material layer to form a pair of bottom select conductor material layers and a bottom opening extending along the vertical direction through the pair of bottom conductor material layers and into the buffer oxide layer and along the horizontal direction; and
depositing a dielectric material to fill up the bottom opening.

4. The method of claim 1 , wherein forming the plurality of conductor layers and the plurality of insulating layers comprise:
depositing, alternatingly, a plurality of conductor material layers and a plurality of insulating material layers on the pair of bottom select conductor material layers; and
etching, repetitively, the pair of bottom select conductor material layers, the plurality of conductor material layers, and the plurality of insulating material layers to form a staircase structure of the pair of bottom select conductor layers, and the interleaved plurality of conductor layers and plurality of insulating layers over the substrate.

5. The method of claim 1 , wherein forming the plurality of conductor layers and the plurality of insulating layers comprises:
depositing, alternatingly, a first plurality of conductor material layers and a first plurality of insulating material layers on the pair of bottom select conductor material layers;
forming a first channel hole extending along the vertical direction through the first plurality of conductor material layers, the first plurality of insulating material layers, and the pair of bottom select conductor material layers and into the substrate, the first channel hole being away from the bottom select structure along another horizontal direction perpendicular to the horizontal direction;
performing a recess etch at the bottom of the first channel hole to expose the substrate;
performing an epitaxial deposition of a semiconductor material to fill up the bottom of the first channel hole, a top surface of the epitaxial portion being between a top surface and a bottom surface of a bottom insulating layer over the pair of bottom select conductor material layers;
forming a sacrificial structure to fill up the first channel hole;
forming a second plurality of conductor material layers and a second plurality of insulating material layers interleaved over the first plurality of conductor material layers, the plurality of insulating material layers, and the sacrificial structures; and
etching, repetitively, the pair of bottom select conductor material layers, the first plurality of conductor material layers, the first plurality of insulating material layers, the second plurality of conductor material layers, the second plurality of insulating materials to form a staircase structure of the first plurality of conductor layers, the first plurality of insulating layers, the second plurality of conductor layers, and the second plurality of insulating layers interleaved over the pair of bottom select conductor layers on the substrate.

6. The method of claim 5 , wherein forming a plurality of channel structures comprises:
forming a second channel hole aligned with the respective first channel hole along the vertical direction, the second channel hole extending along the vertical direction through a dielectric cap layer over the second plurality of conductor material layers and the second plurality of insulating material layers, the second plurality of conductor layers, and the second plurality of insulating layers, and exposing the respective first channel hole and respective sacrificial structure;
removing the sacrificial structure in the first channel hole to expose the epitaxial portion, the first channel hole and the second channel hole forming a channel hole; and
forming a channel-forming structure to fill up the channel hole and performing a recess etch on the channel-forming structure to form the semiconductor channel so that a top surface of the semiconductor channel is between a top surface and a bottom surface of the dielectric cap layer.

7. The method of claim 5 , wherein forming a first top select structure comprises:
patterning the dielectric cap layer to form a first top opening extending along the vertical direction from the top surface of the dielectric cap layer to a first insulating layer under the pair of top select conductor layers and along the horizontal direction, the first top opening being aligned with the bottom select structure along the vertical direction; and
depositing a dielectric material to fill up the first top opening, the dielectric material comprising at least one of silicon oxide, silicon nitride, or silicon oxynitride.

8. The method of claim 7 , further comprising forming at least one second top select structure in a respective memory block by a same process that forms the first top select structure, wherein the at least one second top select structure is formed by:
patterning the dielectric cap layer to form at least one second top opening in the respective memory block with a same patterning process the first top opening is being formed, the at least one second top opening extending along the vertical direction from the top surface of the dielectric cap layer to the first insulating layer and along the horizontal direction; and
depositing the dielectric material to fill up the at least one second top opening and form the at least one second top select structure when the first top opening is being filled with the dielectric material, wherein
the at least one second top select structure divides the respective memory block into a plurality of memory fingers and divides the respective top select conductor layer into a plurality of top select conductor sub-layers, each of the plurality of top select conductor sub-layers corresponding to a respective memory finger.

9. A method for forming a three-dimensional (3D) memory device, comprising:
forming a bottom select structure extending along a horizontal direction and dividing a bottom conductor layer over a substrate into a pair of bottom select conductor layers;
forming a plurality of conductor layers and a plurality of insulating layers interleaved on the pair of bottom select conductor layers and the bottom select structure;
forming a plurali

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Huo Zongliang
• Yang Haohao
• Xu Wei
• Yan Ping
• Huang Pan
• Zhou Wenbin

Classifications

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B41/10 Primary

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title