Electrostatic discharge guard ring with snapback protection

Patent metadata

Field	Value
Publication number	US-11764208-B2
Application number	US-202017123413-A
Country	US
Kind code	B2
Filing date	Dec 16, 2020
Priority date	Oct 12, 2016
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

First claim

What is claimed is:

1. An integrated circuit comprising:
(a) a substrate having a low voltage region and having a high voltage region, the high voltage region including a high voltage circuit region and a peripheral region that circumscribes the high voltage circuit region;
(b) a low voltage circuit formed in the low voltage region;
(c) a high voltage circuit formed in the high voltage circuit region; and
(d) an electrostatic discharge circuit partially formed in the peripheral region, the electrostatic discharge circuit including a bipolar transistor having a collector region, an emitter region, and a base region and including a pinch resistance region having a first end coupled to the base region of the bipolar transistor and having a second end.

2. The integrated circuit of claim 1 in which the emitter region includes an N+ contact region.

3. The integrated circuit of claim 1 in which the collector region includes a buried layer within the high voltage circuit region.

4. The integrated circuit of claim 1 in which the collector region includes an N-type dopant buried layer within the high voltage circuit region.

5. The integrated circuit of claim 1 in which the base region includes a P+ contact region.

6. The integrated circuit of claim 1 in which the peripheral region includes a P+ contact region, an N+ contact region spaced a distance L p from the P+ contact region, a first N-type buried layer in the substrate spaced a distance W p below the P+ contact region and the N+ contact region, and a second N-type buried layer in the substrate in the high voltage circuit region and spaced from the first N-type buried layer.

7. The integrated circuit of claim 6 in which the pinch resistance region includes the P+ contact region and the N+ contact region.

8. The integrated circuit of claim 7 in which the emitter region includes the N+ contact region.

9. The integrated circuit of claim 8 in which the base region is coupled to the pinch resistance region.

10. The integrated circuit of claim 9 in which the collector region includes the second N-type buried layer.

11. The integrated circuit of claim 10 in which the pinch resistance region has a pinch resistance that is proportional to the distance L p of the pinch resistance region and that is inversely proportional to the distance W p of the pinch resistance region.

12. The integrated circuit of claim 1 in which the high voltage circuit region includes a high side gate driver circuit.

13. The integrated circuit of claim 1 in which the low voltage region includes a low voltage control region.

14. The integrated circuit of claim 1 in which the low voltage region includes a low side gate driver circuit.

15. The integrated circuit of claim 1 in which the electrostatic discharge circuit has one of a rectangular profile, an oval profile, and a multi-finger profile.

16. The integrated circuit of claim 1 in which the electrostatic discharge circuit is segmented.

17. The integrated circuit of claim 1 in which the electrostatic discharge circuit is segmented in four segments.

18. An integrated circuit comprising:
(a) a substrate having a low voltage region and having a high voltage region, the high voltage region including a high voltage circuit region and a peripheral region that circumscribes the high voltage circuit region;
(b) a low voltage circuit formed in the low voltage region;
(c) a high voltage circuit formed in the high voltage circuit region; and
(d) an electrostatic discharge circuit partially formed in the peripheral region, the electrostatic discharge circuit including a bipolar transistor having a collector region, an emitter region, and a base region and including a pinch resistance region having a first end coupled to the base region of the bipolar transistor and having a second end, wherein the emitter region includes an N+ contact region, wherein the collector region includes a buried layer within the high voltage circuit region.

19. An integrated circuit comprising:
(a) a substrate having a low voltage region and having a high voltage region, the high voltage region including a high voltage circuit region and a peripheral region that circumscribes the high voltage circuit region;
(b) a low voltage circuit formed in the low voltage region;
(c) a high voltage circuit formed in the high voltage circuit region; and
(d) an electrostatic discharge circuit partially formed in the peripheral region, the electrostatic discharge circuit including a bipolar transistor having a collector region, an emitter region, and a base region and including a pinch resistance region having a first end coupled to the base region of the bipolar transistor and having a second end, wherein the peripheral region includes a P+ contact region, an N+ contact region spaced a distance L p from the P+ contact region, a first N-type buried layer in the substrate spaced a distance Wp below the P+ contact region and the N+ contact region, and a second N-type buried layer in the substrate in the high voltage circuit region and spaced from the first N-type buried layer, and wherein the pinch resistance region has a pinch resistance that is proportional to the distance L p of the pinch resistance region and that is inversely proportional to the distance W p of the pinch resistance region.

20. The integrated circuit of claim 19 in which the electrostatic discharge circuit has one of a rectangular profile, an oval profile, and a multi-finger profile.

Assignees

• Texas Instruments Inc

Inventors

• Kim Sunglyong
• LaFonteese David
• Sridhar Seetharaman
• Pendharkar Sameer

Classifications

• H10D64/111

  Field plates · CPC title

• H10D62/106

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title

• H10D10/40

  Vertical BJTs {(Vertical Heterojunction BJTs H10D10/821)} · CPC title

• H10D84/153

  the built-in component being PN junction diodes · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title