ESD protection device

Patent metadata

Field	Value
Publication number	US-9831232-B2
Application number	US-201615058184-A
Country	US
Kind code	B2
Filing date	Mar 2, 2016
Priority date	Oct 2, 2015
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

An electrostatic protection includes a buried layer having an outer region and an inner region which are heavily doped regions of a first conductivity type. The inner region is surrounded by an undoped or lightly doped ring region. The ring region is surrounded by the outer region. The device further includes a semiconductor region over the buried layer, a first well of the first conductivity type in the semiconductor region, a first transistor in the semiconductor region, and a second transistor in the semiconductor region. The first well forms a collector of the first transistor and a collector of the second transistor.

First claim

The invention claimed is:

1. An electrostatic protection device coupled between a first terminal and a second terminal of an integrated circuit, comprising:
a buried layer having an outer region and an inner region which are heavily doped regions of a first conductivity type, the inner region being surrounded by a ring region which is an undoped or lightly doped ring-shaped region and which is surrounded by the outer region;
a semiconductor region over the buried layer;
a first well of the first conductivity type in the semiconductor region, extending from a surface of the semiconductor region to a main region of the outer region of the buried layer;
a first transistor in the semiconductor region having an emitter coupled to the first terminal; and
a second transistor in the semiconductor region having an emitter coupled to the second terminal,

wherein the first well forms a collector of the first transistor and a collector of the second transistor, and wherein the buried layer is located below at least one of the first transistor and the second transistor.

2. The electrostatic protection device of claim 1 , wherein the buried layer is located below only one of the first transistor and the second transistor.

3. The electrostatic protection device of claim 1 , wherein the inner region of the buried layer is rectangular in a plane parallel to a major surface of the buried layer.

4. The electrostatic protection device of claim 1 , wherein the semiconductor region is of a second conductivity type different from the first conductivity type.

5. The electrostatic protection device of claim 1 , further comprising a substrate and an insulating layer over the substrate, wherein the buried layer and the semiconductor region are located over the insulating layer.

6. The electrostatic protection device of claim 1 , wherein the ring region has a width adapted to maximize a holding voltage of the electrostatic protection device.

7. The electrostatic protection device of claim 1 , comprising:
a first trigger region of a second conductivity type different from the first conductivity type and in contact with the first transistor and the semiconductor region;
a first shallow trench isolation structure in contact with the first well and the semiconductor region;
wherein the semiconductor region includes a first gap region located between the first trigger region and the first shallow trench isolation structure and having a width similar to a width of the ring region.

8. The electrostatic protection device of claim 1 , comprising:
a second trigger region of a second conductivity type different from the first conductivity type and in contact with the second transistor and the semiconductor region;
a second shallow trench isolation structure in contact with the first well and the semiconductor region;
wherein the semiconductor region includes a second gap region located between the second trigger region and the second shallow trench isolation structure and having a width similar to a width of the ring region.

9. The electrostatic protection device of claim 1 , wherein the area of the inner region parallel to a major surface of the buried layer is between 25% and 45% of the area of the outer region parallel to the major surface of the buried layer.

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Hong Changsoo
• Besse Patrice
• Laine Jean Philippe
• Zhan Rouying

Classifications

• H01L29/0804

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L29/7436

  Electricity · mapped topic

• H01L27/0727

  Electricity · mapped topic

• H01L29/0623

  Electricity · mapped topic