Diffusion soldering preform with varying surface profile

Patent metadata

Field	Value
Publication number	US-11764185-B2
Application number	US-202117462573-A
Country	US
Kind code	B2
Filing date	Aug 31, 2021
Priority date	Aug 31, 2021
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

A method of soldering includes providing a substrate having a first metal joining surface, providing a semiconductor die having a second metal joining surface, providing a solder preform having a first interface surface and a second interface surface, arranging the solder preform between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface, and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the solder. One or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.

First claim

What is claimed is:

1. A method of soldering a semiconductor device, the method comprising:
providing a substrate comprising a first metal joining surface;
providing a semiconductor die comprising a second metal joining surface;
providing a solder preform that comprises a first interface surface and a second interface surface opposite the first interface surface;
arranging the solder preform in between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface; and
performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the soldered joint;
wherein one or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.

2. The method of claim 1 , wherein the varying surface profile comprises a plurality of ridges and channels that are disposed between immediately adjacent ones of the ridges, and wherein the channels create the voids in the arrangement of the solder preform in between the substrate and the semiconductor die.

3. The method of claim 2 , wherein at least one of the channels laterally extends completely between two edge sides of the solder preform.

4. The method of claim 2 , wherein at least one of the channels laterally extends from one edge side of the solder preform to a central region of the solder preform, wherein the central region is spaced apart from every edge side of the solder preform by at least 1 mm.

5. The method of claim 2 , wherein the ridges and channels have an undulating profile along a cross-section of the solder preform that is orthogonal to the ridges.

6. The method of claim 5 , wherein both of the first interface surface and the second interface surface have the same undulating profile, and wherein the solder preform has a substantially uniform thickness along the cross-section of the solder preform that is orthogonal to the ridges.

7. The method of claim 2 , wherein a thickness of the solder perform is between 5 μm and 15 μm.

8. The method of claim 7 , wherein a separation distance between two immediately adjacent ones of the ridges is between two and fifty times the thickness of the solder preform.

9. The method of claim 8 , wherein the varying surface profile is such that a plurality of the ridges are regularly spaced apart from one another by a fixed separation distance that is between two and fifty times the thickness of the solder preform.

10. The method of claim 7 , wherein a maximum vertical displacement of the solder preform between the first interface surface and the second interface surface is between four times the thickness of the solder preform and ten times the thickness of the solder preform.

11. The method of claim 1 , wherein the solder preform comprises Sn, Zn, In, Ga, Bi, Cd or any alloy thereof.

12. The method of claim 1 , wherein performing the mechanical pressure-free diffusion soldering process comprises a conditioning step that removes a tacking agent from the arrangement of the solder preform in between the substrate and the semiconductor die.

13. The method of claim 1 , wherein performing the mechanical pressure-free diffusion soldering process comprises an activation step that introduces formic acid into a soldering furnace that contains the arrangement of the solder preform in between the substrate and the semiconductor die.

14. A method of soldering a semiconductor device, the method comprising:
providing a substrate comprising a first metal joining surface;
providing a semiconductor die comprising a second metal joining surface;
providing a solder preform that comprises a first interface surface and a second interface surface opposite the first interface surface;
arranging the solder preform in between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface;
placing the arrangement of the solder preform in between the substrate and the semiconductor die in a soldering furnace;
performing one or more pre-soldering steps in the soldering furnace below a reflow temperature of the solder preform with the arrangement of the solder preform contained in the soldering furnace;
increasing the temperature of the soldering furnace to reach a melting temperature of the solder preform such that the solder preform melts and reacts with the first and second metal joining surfaces to form intermetallic phases in a soldered joint without applying mechanical pressure to the arrangement,
wherein during the pre-soldering steps the arrangement of the solder preform in between the substrate and the semiconductor die comprises channels between the solder preform and one or both of the substrate and the semiconductor die, and
wherein the channels permit ingress and egress of ambient atmosphere within the soldering furnace.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Trunov Kirill
• Hendrix Thomas

Classifications

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/225

  Bumps having a filler embedded in a matrix · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/0198

  batch processes · CPC title