Semiconductor device including bonding pad metal layer structure

Patent metadata

Field	Value
Publication number	US-11764176-B2
Application number	US-202117400303-A
Country	US
Kind code	B2
Filing date	Aug 12, 2021
Priority date	Aug 18, 2020
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a wiring metal layer structure;
a dielectric layer structure arranged directly on the wiring metal layer structure; and
a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure,
wherein a layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure,
wherein the wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure,
wherein the bonding pad metal layer structure or a portion of the bonding pad metal layer comprises Al by at least 50% of the amount of substance.

2. The semiconductor device of claim 1 , wherein the wiring metal layer structure or a portion of the wiring metal layer structure comprises Al by at least 50% of the amount of substance.

3. The semiconductor device of claim 1 , wherein the wiring metal layer structure or the portion of the wiring metal layer structure includes a first metal compound of at least Cu and Al, or AlSiCu.

4. The semiconductor device of claim 1 , wherein the bonding pad metal layer structure or the portion of the bonding pad metal layer includes a second metal compound of at least Cu and Al.

5. The semiconductor device of claim 1 , wherein the wiring metal layer structure or the portion of the wiring metal layer structure includes AlSiCu, and wherein the bonding pad metal layer structure or the portion of the bonding pad metal layer structure includes AlCu.

6. The semiconductor device of claim 1 , wherein the layer thickness of the dielectric layer structure ranges from 50 nm to 1 μm.

7. The semiconductor device of claim 1 , wherein a lateral end of the dielectric layer structure laterally protrudes from a lateral end of the bonding pad metal layer structure.

8. The semiconductor device of claim 1 , further comprising a passivation layer structure arranged between the dielectric layer structure and the wiring metal layer structure in a peripheral part of the dielectric layer structure.

9. The semiconductor device of claim 1 , further comprising a semiconductor body, wherein the wiring metal layer structure directly adjoins a surface of the semiconductor body.

10. The semiconductor device of claim 1 , wherein the dielectric layer structure comprises any one of or any combination of an oxide layer, a silicon oxynitride layer, a nitride layer, and an undoped polycrystalline silicon layer.

11. The semiconductor device of claim 1 , wherein the semiconductor device is a power semiconductor device.

12. The semiconductor device of claim 1 , wherein the bonding pad metal layer structure includes a central part and a peripheral part, and wherein any wire bond on the bonding pad metal layer structure is located in the central part.

13. The semiconductor device of claim 12 , wherein a number of wire bonds on the bonding pad metal layer structure is equal to two or larger.

14. The semiconductor device of claim 12 , wherein the dielectric layer structure includes a closed peripheral part.

15. The semiconductor device of claim 14 , wherein the dielectric layer structure includes a central part that is laterally spaced from the closed peripheral part by a separative opening in the dielectric layer structure.

16. The semiconductor device of claim 15 , wherein a maximum lateral extent of the openings in the central part of the dielectric layer structure is smaller than a sum of the layer thickness of the wiring metal layer structure and the layer thickness of the bonding pad metal layer structure.

17. The semiconductor device of claim 15 , wherein a minimum lateral extent of the openings in the central part of the dielectric layer structure is equal to or larger than two times the layer thickness of the dielectric layer structure.

18. The semiconductor device of claim 15 , wherein the dielectric layer structure covers 25% to 90% of a bottom of the bonding pad metal layer structure in the central part of the bonding pad metal layer structure.

Assignees

• Infineon Technologies Ag

Inventors

• Napetschnig Evelyn
• Brandenburg Jens
• Erbert Christoffer
• Hirschler Joachim
• Humbel Oliver
• Rupp Thomas
• Schaeffer Carsten
• Zischang Julia

Classifications

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W20/4424

  Copper alloys · CPC title

• H10W20/4407

  Aluminium alloys · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title