Printed circuit and circuit board assembly configured for quad signaling
US-2017196079-A1 · Jul 6, 2017 · US
Backplane footprint for high speed, high density electrical connectors
US11758656B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11758656-B2 |
| Application number | US-202117347668-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 15, 2021 |
| Priority date | Jun 11, 2018 |
| Publication date | Sep 12, 2023 |
| Grant date | Sep 12, 2023 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A printed circuit board includes a plurality of layers including conductive layers separated by dielectric layers; and at least one via configured for solder attachment to a connector lead of a surface mount connector, the at least one via including a conductive element that extends from an upper surface of the printed circuit board through one or more of the plurality of layers, the conductive element having a recess in a surface thereof. The recess is configured to receive a tip portion of the connector lead of the surface mount connector. The printed circuit board may have via patterns including signal vias and ground vias.
First claim
Opening claim text (preview).
What is claimed is: 1. An interconnection system comprising: a surface mount component comprising surface mount leads; and a printed circuit board comprising conductive layers separated by dielectric layers, and vias configured for solder attachment to respective leads of the surface mount component, each of the vias including a conductive element having a recess in an upper surface thereof, wherein the recess in the conductive element is smaller in diameter than a surface mount lead of the surface mount leads and receives only a tip portion of the surface mount lead. 2. The interconnection system as defined in claim 1 , wherein tip portions of the surface mount leads are configured to be inserted into respective recesses of the printed circuit board. 3. The interconnection system as defined in claim 1 , wherein the recess includes at least one of a conical portion, a truncated conical portion, a cylindrical portion and a hemispherical portion. 4. The interconnection system as defined in claim 1 , wherein the surface mount connector leads comprise superelastic components. 5. The interconnection system as defined in claim 1 , wherein at least 95% of the surface mount leads comprise distal tips extending into respective recesses. 6. The interconnection system as defined in claim 1 , wherein the recess has a depth in a range of 0.05 mm to 0.30 mm.
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Frequently asked questions
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- What does patent US11758656B2 cover?
- A printed circuit board includes a plurality of layers including conductive layers separated by dielectric layers; and at least one via configured for solder attachment to a connector lead of a surface mount connector, the at least one via including a conductive element that extends from an upper surface of the printed circuit board through one or more of the plurality of layers, the conductive…
- Who is the assignee on this patent?
- Amphenol Corp
- What technology area does this patent fall under?
- Primary CPC classification H01R12/57. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 12 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).