Techniques for escalating interrupts in a data processing system to a higher software stack level

Patent metadata

Field	Value
Publication number	US-9792233-B2
Application number	US-201615339469-A
Country	US
Kind code	B2
Filing date	Oct 31, 2016
Priority date	Nov 16, 2015
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

A technique for escalating interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM) that specifies a level, an event target number, a number of bits to ignore, and an event priority. A group of virtual processor threads that may be potentially interrupted is determined based on the event target number, the number of bits to ignore, the level, and a process identifier (ID) when the level specified in the ENM corresponds to a user level. In response to the event priority in the ENM not being greater than an operating priority of at least one virtual processor thread in the group of virtual processor threads, an escalate message that includes an escalate event number (EEN), sourced from an interrupt context table of the IPC, is issued. The EEN is used by an interrupt source controller to generate another ENM.

First claim

What is claimed is:

1. A method of escalating interrupts in a data processing system, the method comprising:
receiving, at an interrupt presentation controller (IPC), a first event notification message (ENM), wherein the first ENM specifies a level, an event target number, a number of bits to ignore, and an event priority;
determining, by the IPC, a group of virtual processor threads that may be potentially interrupted based on the event target number, the number of bits to ignore, the level, and a process identifier (ID) when the level specified in the first ENM corresponds to a user level, wherein the event target number in the first ENM identifies a specific virtual processor thread, the number of bits to ignore in the first ENM identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining the group of virtual processor threads that may be potentially interrupted, and the level in the first ENM specifies a first software stack level;
in response to at least one virtual processor thread within the group of virtual processor threads being dispatched and operating on an associated physical processor, determining, by the IPC, whether the event priority in the first ENM is greater than an operating priority of the at least one virtual processor thread; and
in response to the event priority in the first ENM not being greater than an operating priority of the at least one virtual processor thread, issuing, by the IPC, a first escalate message that includes a first escalate event number that is sourced from an interrupt context table (ICT) of the IPC, wherein the first escalate event number is used by an interrupt source controller (ISC) to generate a second ENM that targets a second software stack level that is different than the first software stack level.

2. The method of claim 1 , wherein the first ENM further includes a second escalate event number and the method further comprises:
in response to no virtual processor thread within the group of virtual processor threads being dispatched and operating on an associated physical processor, issuing a second escalate message that includes the second escalate event number to the ISC, wherein the second escalate event number is used by the ISC to generate a third ENM that targets a third software stack level that is different than the first software stack level.

3. The method of claim 1 , wherein the process ID is not used when the level corresponds to an operating system (OS) level or a hypervisor level.

4. The method of claim 1 , wherein the number of bits to ignore is ‘n’ bits and the specific virtual processor thread and (2 n −1) other virtual processor threads may be potentially interrupted.

5. The method of claim 1 , wherein the number of bits to ignore is not equal to zero, the first ENM further includes an event source number, and the method further comprises:
in response to no virtual processor thread within the group of virtual processor threads being dispatched and operating on an associated physical processor, issuing a reject message to a notification source specified by the event source number.

6. The method of claim 1 , wherein the number of bits to ignore is not equal to zero and the method further comprises:
in response to multiple virtual processor threads within the group of virtual processor threads being dispatched and operating on an associated physical processor, selecting one of the multiple virtual processor threads to interrupt that does not already have a pending interrupt.

7. The method of claim 6 , further comprising:
in response to more than one of the multiple virtual processor threads not already having a pending interrupt, selecting one of the multiple virtual processor threads to interrupt that does not already have a pending interrupt based on secondary selection criteria.

8. The method of claim 7 , wherein the secondary selection criteria includes one or more of the event priority relative to an operating priority for each of the multiple virtual processor threads, a least recently used (LRU) one of the multiple virtual processor threads, and a random one of the multiple virtual processor threads.

9. The method of claim 1 , wherein the number of bits to ignore is not equal to zero, the first ENM further includes an event source number, and the method further comprises:
in response to multiple virtual processor threads within the group of virtual processor threads being dispatched and operating on an associated physical processor, determining whether all of the multiple processor threads have pending interrupts;
in response to determining that all of the multiple processor threads have pending interrupts, determining whether the event priority of the first ENM is greater than an operating priority of any of the multiple virtual processor threads; and
in response to determining that the event priority of the first ENM is not greater than the operating priority of any of the multiple virtual processor threads, issuing a reject message to a notification source specified by the event source number in the first ENM.

10. The method of claim 9 , further comprising:
in response to determining that the event priority of the first ENM is greater than the operating priority of any of the multiple virtual processor threads, selecting one of the multiple virtual processor threads to interrupt that has an operating priority less than the event priority.

11. The method of claim 9 , further comprising:
in response to determining that the event priority of the first ENM is greater than the operating priority of more than one of the multiple virtual processor threads, selecting one of the multiple virtual processor threads to interrupt that has an operating priority less than the event priority based on secondary selection criteria.

12. The method of claim 11 , wherein the secondary selection criteria includes one or more of the event priority relative to an operating priority for the multiple virtual processor threads, a least recently used (LRU) one of the multiple virtual processor threads, and a random one of the multiple virtual processor threads.

13. A processing unit for a multithreaded data processing system, the processing unit comprising:
an interrupt source controller (ISC); and
an interrupt presentation controller (IPC) coupled to the ISC, wherein the IPC is configured to:
receive a first event notification message (ENM) from the ISC, wherein the first ENM specifies a level, an event target number, a number of bits to ignore, and an event priority;
determine a group of virtual processor threads that may be potentially interrupted based on the event target number, the number of bits to ignore, the level, and a process identifier (ID) when the level specified in the first ENM corresponds to a user level, wherein the event target number in the first ENM identifies a specific virtual processor thread, the number of bits to ignore in the first ENM identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining the group of virtual processor threads that may be potentially interrupted, and the level in the first ENM specifies a first software stack level;
in response to at least one virtual processor thread within the group of virtual processor threads being dispatched and operating on an associated physical processor, determine whether the event priority in the first ENM is greater than an operating priority of the at least one virtual processor thread; and
in response to the event priority in the first ENM not being greater than an operating priority of the at

Assignees

• IBM
• IBM

Inventors

• Arndt Richard L
• Auernhammer Florian A

Classifications

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F12/12

  Replacement control · CPC title

• G06F2212/70

  Details relating to dynamic memory management · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title