Processor frequency improvement based on antenna optimization

Patent metadata

Field	Value
Publication number	US-11754615-B2
Application number	US-202117480551-A
Country	US
Kind code	B2
Filing date	Sep 21, 2021
Priority date	Sep 21, 2021
Publication date	Sep 12, 2023
Grant date	Sep 12, 2023

Abstract

A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.

First claim

What is claimed is:

1 . A method of increasing processor frequency in an integrated circuit (IC), the method comprising:
identifying a gate included in the IC, the gate having a gate threshold voltage; performing a plasma process to form an antenna signal path in signal communication with the gate; and adjusting the plasma process to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.

2 . The method of claim 1 , wherein altering the gate threshold voltage includes one of increasing or decreasing the gate threshold voltage to increase a switching speed of the gate.

3 . The method of claim 2 , wherein the plasma process includes a plasma etching process.

4 . The method of claim 3 , wherein adjusting the plasma process includes one or more of increasing plasma etch flux levels, increasing plasma etch duration times, and varying thicknesses of oxide materials located in non-etching regions.

5 . The method of claim 2 , wherein the plasma process includes a plasma deposition process.

6 . The method of claim 5 , wherein adjusting the plasma process includes one or more of increasing plasma deposition quantity levels and increasing plasma deposition duration times.

7 . The method of claim 2 , further comprising:
performing a timing validation run on the gate having the altered gate voltage threshold; determining a timing violation of the gate having the altered gate voltage threshold based on the timing validation run; and replacing the gate with the altered gate voltage to remove the timing violation.

8 . The method of claim 7 , wherein determining the timing violation comprises:
storing at least one timing threshold corresponding to one or both of the antenna signal path and the gate; comparing a timing result obtained from the timing validation run to the at least one timing threshold; and determining the timing violation in response to the at least one timing result exceeding the at least one timing threshold.

9 . A system configured to fabricate an integrated circuit (IC) having an increased processor frequency, the system comprising:
memory configured to store at least one timing requirement corresponding to one or both of an antenna signal path and a plasma induced damaged (PID)-altered gate formed according to a plasma process; and a processor configured to perform a timing validation run on the PID-altered gate and to determine timing results associated with the PID-altered gate in response to the timing validation run, and to determine a timing violation based on a comparison between the timing results and the timing requirement, wherein one or both of the antenna signal path and the PID-altered gate are replaced to remove the timing requirement.

10 . The system of claim 9 , wherein the timing requirements include at least one timing threshold corresponding to one or both of a given antenna signal path and a given gate.

11 . The system of claim 10 , wherein the timing violation is detected in response to the timing results exceeding the at least one timing threshold.

12 . The system of claim 11 , wherein the timing requirements are expressed as a model indicating a time duration at which it takes for a first component to charge or discharge a given wireload and pass a logic “1” value or a logic “0” value on to a second component, and wherein the timing violation is detected in response to the time duration exceeding the at least one timing threshold.

13 . The system of claim 9 , wherein the plasma process includes a plasma etching process.

14 . The system of claim 9 , wherein the plasma process includes a plasma deposition process.

15 . A method of increasing processor frequency in an integrated circuit (IC), the method comprising:
identifying in the IC a gate and a corresponding antenna signal path, the gate having a gate threshold voltage; performing a plasma induced damage PID design exploitation to optimize a ratio between a metal area corresponding to the antenna signal path and a gate area corresponding to the gate; and forming the gate and the antenna signal path on a wafer based on the optimized ratio, wherein the optimized ratio increases a level of plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage when forming the gate and the antenna signal path.

16 . The method of claim 15 , wherein the optimized ratio includes performing at least one of: varying the metal area of the antenna signal path, varying an aspect ratio of the antenna signal path, and varying the gate area of the gate.

17 . The method of claim 16 , wherein forming one or both of the gate and the antenna signal path according to the optimized ratio includes performing a plasma process that produces the plasma induced damage.

18 . The method of claim 16 , wherein performing the PID design exploitation further includes:
predetermining an initial manufactured gate threshold voltage of the gate; determining different levels of altered gate threshold voltages that occur in response to adjusting one or more antenna ratios of the gate; determining a target gate threshold voltage of the gate; and performing one or more of varying the metal area of the antenna signal path, varying the aspect ratio of the antenna signal path, and varying the gate area of the gate to change the gate threshold voltage to the target gate threshold voltage.

19 . The method of claim 18 , wherein the gate threshold voltage has a first value and the target gate threshold voltage has a second voltage that is less than the first value of the gate threshold voltage.

20 . The method of claim 19 , wherein the antenna ratio of the gate is a ratio of the metal area with respect to a combination of the gate area and a ratio RX diffusion of the gate area.

Assignees

• IBM

Inventors

• Gonzalez Christopher
• Wolpert David
• Wood Michael Hemsley

Classifications

• G06F30/337 Primary

  Design optimisation · CPC title

• G01R31/2623 Primary

  for measuring break-down voltage therefor · CPC title

• G06F2117/12

  Sizing, e.g. of transistors or gates · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/3312

  Timing analysis · CPC title