Integrated circuit devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11749734-B2
Application number	US-202218087854-A
Country	US
Kind code	B2
Filing date	Dec 23, 2022
Priority date	May 25, 2020
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

An integrated circuit device includes a fin-type active area that extends on a substrate in a first direction, a gate structure that extends on the substrate in a second direction and crosses the fin-type active area, source/drain areas arranged on first and second sides of the gate structure, and a contact structure electrically connected to the source/drain areas. The source/drain areas comprise a plurality of merged source/drain structures. Each source/drain area comprises a plurality of first points respectively located on an upper surface of the source/drain area at a center of each source/drain structure, and each source/drain area comprises at least one second point respectively located on the upper surface of the source/drain area where side surfaces of adjacent source/drain structures merge with one another. A bottom surface of the contact structure is non-uniform and corresponds to the first and second points.

First claim

What is claimed is:

1. A method of manufacturing an integrated circuit device, the method comprising:
forming a fin-type structure that extends in a first direction on a substrate and forming a channel area on the fin-type structure;
forming a gate structure that extends on the substrate in a second direction and that crosses with the fin-type structure;
forming a merged source/drain structure on a side of the gate structure;
forming an etch stop layer on the merged source/drain structure;
partially etching an upper surface of the merged source/drain structure to have a wavy shape by using a residual stop layer as an etch mask;
forming a silicide layer on an etched portion of the merged source/drain structure; and
forming a contact structure electrically connected to the merged source/drain structure and having a bottom surface that corresponds to the wavy shape of the upper surface of the merged source/drain structure.

2. The method of claim 1 , wherein the silicide layer is formed under the contact structure at the etched portion of the merged source/drain structure, and
wherein the residual stop layer is formed under the contact structure in a portion where the merged source/drain structure is not etched.

3. The method of claim 1 , wherein a lowermost level of the silicide layer is lower than a lowermost level of the residual stop layer.

4. The method of claim 1 , wherein a length of the silicide layer in the second direction is greater than a length of the residual stop layer in the second direction.

5. The method of claim 1 , wherein the silicide layer and the residual stop layer are alternately formed in the second direction.

6. The method of claim 1 , wherein the forming of the silicide layer comprises:
forming a barrier metal layer on the merged source/drain structure and the residual stop layer; and
performing a heat treatment process.

7. The method of claim 6 , wherein the barrier metal layer comprises a material that reacts with a material of the merged source/drain structure as a result of the heat treatment process.

8. The method of claim 6 , wherein the forming of the contact structure comprises forming a contact metal layer on the barrier metal layer.

9. The method of claim 1 , wherein a phase of the upper surface of the merged source/drain structure is substantially identical to a phase of a lower surface of the contact structure.

10. The method of claim 1 , wherein the fin-type structure and the silicide layer are aligned in a vertical direction.

11. A method of manufacturing an integrated circuit device, the method comprising:
forming a plurality of fin-type structures and a plurality of channel areas that protrude from a substrate;
forming a gate structure crossing the plurality of fin-type structures;
forming a merged source/drain structure having a wavy upper surface on a first side of the gate structure;
alternately forming a silicide layer and a residual stop layer on the merged source/drain structure along the wavy upper surface; and
forming a contact structure electrically connected to the merged source/drain structure.

12. The method of claim 11 , wherein a number of the fin-type structures in contact with the merged source/drain structure is equal to a number of silicide layers arranged on the merged source/drain structure.

13. The method of claim 12 , wherein a lower surface of the contact structure is formed along the wavy upper surface, and
wherein a lowest point of the lower surface of the contact structure is formed on an upper portion of the fin-type structure.

14. The method of claim 11 , wherein the forming of the contact structure comprises:
forming a barrier metal layer on the merged source/drain structure and the residual stop layer; and
forming a contact metal layer on the barrier metal layer.

15. The method of claim 14 , wherein the residual stop layer, the barrier metal layer, and the contact metal layer are sequentially formed in a vertical direction along the upper surface of the merged source/drain structure.

16. A method of manufacturing an integrated circuit device, the method comprising:
forming a plurality of fin-type structures and a plurality of channel areas extending in a first direction on a substrate;
forming a gate structure extending on the substrate in a second direction intersecting with the fin-type structures;
forming a merged source/drain structure on a first side of the gate structure and arranged on the plurality of fin-type structures;
forming an etch stop layer covering the merged source/drain structure;
forming an interlayer insulating layer that covers the etch stop layer;
forming a contact hole that extends into the interlayer insulating layer;
forming a residual stop layer by partially etching the etch stop layer;
partially etching an upper surface of the merged source/drain structure to have a wavy shape by using the residual stop layer as an etch mask;
forming a barrier metal layer along the contact hole and performing heat treatment to form a silicide layer under the barrier metal layer; and
forming a contact metal layer filling the contact hole.

17. The method of claim 16 , wherein the barrier metal layer is formed along the wavy shape of the merged source/drain structure and an upper surface of the residual stop layer.

18. The method of claim 16 , wherein the barrier metal layer includes titanium, and
wherein the contact metal layer includes tungsten.

19. The method of claim 18 , wherein the silicide layer is formed of a combination of a material included in the barrier metal layer and a material included in the merged source/drain structure.

20. The method of claim 16 , wherein the residual stop layer includes silicon nitride or silicon oxynitride.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Sanghyun
• Kang Sungwoo
• Park Jongchul
• Oh Youngmook
• Lee Jeongyun

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title