Raised source/drain EPI with suppressed lateral EPI overgrowth

Patent metadata

Field	Value
Publication number	US-9236452-B2
Application number	US-201414286400-A
Country	US
Kind code	B2
Filing date	May 23, 2014
Priority date	May 23, 2014
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

A method of forming raised S/D regions by partial EPI growth with a partial EPI liner therebetween and the resulting device are provided. Embodiments include forming groups of fins extending above a STI layer; forming a gate over the groups of fins; forming a gate spacer on each side of the gate; forming a raised S/D region proximate to each spacer on each fin of the groups of fins, each raised S/D region having a top surface, vertical sidewalls, and an undersurface; forming a liner over and between each raised S/D region; removing the liner from the top surface of each raised S/D region and from in between a group of fins; forming an overgrowth region on the top surface of each raised S/D region; forming an ILD over and between the raised S/D regions; and forming a contact through the ILD, down to the raised S/D regions.

First claim

What is claimed is:

1. A method comprising:
forming a first group and a second group of fins extending above a shallow trench isolation (STI) layer, the STI layer surrounding at least a portion of the first group and second group of fins;
forming a gate over the first and second groups of fins;
forming a gate spacer on each side of the gate;
subsequent to forming the gate spacer on each side of the gate, forming a raised source/drain (S/D) region proximate to each spacer on each fin of the first and second groups of fins, each raised S/D region having a top surface, vertical sidewalls, and an undersurface;
forming a liner atop and between each raised S/D region;
removing the liner from the top surface of each raised S/D region and from in between the second group of fins;
subsequent to removing the liner, forming an overgrowth region on the top surface of each raised S/D region;
subsequent to forming the overgrowth region on the top surface of each raised S/D region, forming an interlayer dielectric (ILD) over and between the raised S/D regions; and
forming a contact through the ILD, down to the raised S/D regions.

2. The method according to claim 1 , comprising forming the first group of fins with a narrow fin pitch relative to the second group of fins.

3. The method according to claim 1 , comprising forming the raised S/D region by partial epitaxial growth, wherein the sidewalls have a vertical plane greater than or equal to 5 nanometers (nm) in length.

4. The method according to claim 3 , comprising forming the raised S/D region of silicon germanium (SiGe), silicon phosphorous (SiP), silicon carbon phosphorous (SiCP), or silicon carbon boron (SiCB).

5. The method according to claim 3 , comprising forming the raised S/D region at a temperature of 500° C. to 800° C.

6. The method according to claim 3 , comprising forming the raised S/D region for 0.5 minutes to 60 minutes.

7. The method according to claim 3 , comprising forming the raised S/D region at a pressure of 1 Torr to 500 Torr.

8. The method according to claim 1 , comprising forming the liner to a thickness of 25 angstroms (Å) to 150 Å.

9. The method according to claim 8 , comprising forming the liner of silicon nitride (SiN), silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), silicon oxynitride (SiON), silicon-carbon-boron-nitrogen (SiCBN), silicon-carbon-oxynitride (SiCON), silicon carbon nitride (SiCN), or silicon boron nitride (SiBN).

10. The method according to claim 1 , comprising removing the liner by dry or wet etching.

11. The method according to claim 1 , comprising forming the overgrowth region by epitaxial growth.

12. The method according to claim 11 , comprising forming the overgrowth region to a thickness of 20 Å to 300 Å.

13. The method according to claim 1 , comprising forming the overgrowth region of one or more layers of Si, silicon germanium (SiGe), and/or silicon carbide (SiC).

14. The method according to claim 1 , further comprising replacing the gate with a replacement metal gate (RMG) prior to forming the contact by:
forming a polysilicon (poly) dummy gate over the first and second group of fins;
forming a gate hard mask layer on top of the poly dummy gate;
forming the gate spacer on each side of the poly dummy gate;
forming the ILD layer over and between the raised S/D regions;
removing the poly dummy gate, forming a trench between the gate spacers;
forming the replacement metal gate in the trench.

15. A method comprising:
forming a first group and a second group of fins above a shallow trench isolation (STI) layer, the STI layer surrounding at least a portion of the first group and second group of fins;
forming a gate over the first and second group of fins;
forming a gate spacer on each side of the gate;
subsequent to forming the gate spacer on each side of the gate, forming a raised source/drain (S/D) region proximate to each spacer on each fin of the first and second groups of fins by partial epitaxial growth, the S/D region having a top surface, vertical sidewalls, and an undersurface, and wherein the sidewalls have a vertical plane greater than or equal to 5 nanometers (nm) in length;
forming a liner to a thickness of 25 angstroms (Å) to 150 Å atop and between each raised S/D region;
etching the liner from the top surface of each raised S/D region and from in between the second group of fins;
subsequent to etching the liner, forming an epitaxial overgrowth region to a thickness of 20 Å to 300 Å on the top surface of each raised S/D region;
subsequent to forming the epitaxial overgrowth region on the top surface of each raised S/D region, forming an interlayer dielectric (ILD) layer over and between the raised S/D regions; and
forming a contact between the ILD, down to the raised S/D regions.

Assignees

• Globalfoundries Inc

Inventors

• Lim Kwan-Yong
• Fronheiser Jody
• Prindle Christopher

Classifications

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title