Method of fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-10355000-B2
Application number	US-201715793442-A
Country	US
Kind code	B2
Filing date	Oct 25, 2017
Priority date	Apr 3, 2017
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
patterning an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant;
performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region;
doping the first source/drain region with gallium;
performing an annealing process on the first source/drain region doped with gallium; and
forming a first contact pattern coupled to the first source/drain region,
wherein the first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant,
wherein the forming of the first contact pattern comprises:
forming an interlayered insulating layer on the substrate to cover the first source/drain region;
forming a contact hole to penetrate the interlayered insulating layer and to expose the first source/drain region;
forming a barrier layer in the contact hole; and
forming a conductive layer in the contact hole, and
wherein the forming of the first contact pattern further comprises forming a contact spacer layer to fill a portion of the contact hole, and
the doping of the first source/drain region with gallium is performed on the contact spacer layer.

2. A method of fabricating a semiconductor device, comprising:
forming a first device isolation layer on a PMOSFET region of a substrate to define a first active pattern, an upper portion of the first active pattern vertically protruding above the device isolation layer;
forming a gate electrode to cross the first active pattern;
performing a selective epitaxial growth process on the first active pattern adjacent to a side of the gate electrode to form a first source/drain region;
doping the first source/drain region with gallium;
performing an annealing process on the first source/drain region doped with gallium; and
forming a first contact pattern coupled to the first source/drain region,
wherein the first source/drain region has a maximum width, when measured in a direction parallel to a top surface of the substrate, at a first level, and
a bottom surface of the first contact pattern is positioned at a level that is higher than the first level and is lower than a bottom surface of the gate electrode.

3. The method of claim 2 , wherein the substrate includes silicon (Si), and the first source/drain region includes silicon-germanium (SiGe).

4. The method of claim 2 , further comprising selectively etching the first active pattern adjacent to the side of the gate electrode to form a recess region,
wherein the selective epitaxial growth process is performed using the recess region as a seed layer, and
the first source/drain region is formed to fill the recess region.

5. The method of claim 2 , wherein the doping of the first source/drain region with gallium is performed after the forming of the first source/drain region.

6. The method of claim 2 , wherein the doping of the first source/drain region with gallium is performed in an in-situ manner during the forming of the first source/drain region.

7. The method of claim 2 , further comprising forming a gate dielectric pattern between the first active pattern and the gate electrode,
wherein the first contact pattern is formed to have a bottom surface lower than the gate dielectric pattern.

8. The method of claim 2 , further comprising:
forming a second device isolation layer on an NMOSFET region of the substrate to define a second active pattern, an upper portion of the second active pattern vertically protruding above the second device isolation layer;
performing a selective epitaxial growth process on the second active pattern adjacent to a side of the gate electrode to form a second source/drain region; and
forming a second contact pattern coupled to the second source/drain region,
wherein the gallium is selectively doped in the first source/drain region, except for the second source/drain region.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Kyungin
• Kim Taehyeon
• Shin Hongshik
• Kim Taegon
• Park Jaeyoung
• Sasaki Yuichiro

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/076 Primary

  in via holes or trenches · CPC title