Semiconductor memory devices including separate upper and lower bit line spacers and methods of forming the same

Patent metadata

Field	Value
Publication number	US-11744063-B2
Application number	US-202117374624-A
Country	US
Kind code	B2
Filing date	Jul 13, 2021
Priority date	Apr 3, 2017
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

First claim

What is claimed:

1. A method of forming a volatile memory device, the method comprising:
forming a bit line structure having a vertical sidewall protruding from a substrate;
forming a lower spacer layer on the vertical sidewall to have a first thickness;
removing the lower spacer layer from the substrate adjacent to the bit line structure to form a lower spacer having the first thickness from the vertical sidewall to an outer sidewall of the lower spacer;
forming a storage node contact plug on the substrate aligned to the lower spacer to cover the outer sidewall of the lower spacer and to expose an upper portion of the lower spacer;
removing the upper portion of the lower spacer using the storage node contact plug as a mask; and
forming an upper spacer on the vertical sidewall to expose an uppermost portion of the outer sidewall of the lower spacer, the upper spacer formed to have a second thickness that is less than the first thickness,
wherein the upper spacer extends in a vertical direction, and a bottom-most surface of the upper spacer is offset above an uppermost surface of the storage node contact plug, such that the bottom-most surface of the upper spacer does not abut the uppermost surface of the storage node contact plug.

2. The method of claim 1 , wherein the forming the upper spacer further comprises removing the upper spacer from the storage node contact plug and the outer sidewall of the lower spacer to expose an uppermost portion of the lower spacer.

3. The method of claim 2 , wherein the lower spacer layer comprises a first sub-spacer on the vertical sidewall and a second sub-spacer on the first sub-spacer, and
wherein removing the upper portion of the lower spacer comprises removing the upper portion of the lower spacer using the storage node contact plug as the mask to expose at least a portion of the uppermost portion of the lower spacer including the first sub-spacer and the second sub-spacer and to cover a remaining portion of the uppermost portion of the lower spacer.

4. The method of claim 1 ,
wherein the lower spacer layer comprises a first sub-spacer on the vertical sidewall and a second sub-spacer on the first sub-spacer, and
wherein the forming the upper spacer further comprises removing the upper spacer from the storage node contact plug and the outer sidewall of the lower spacer to completely cover an uppermost surface of the lower spacer.

5. The method of claim 1 , wherein the lower spacer layer comprises a first sub-spacer on the vertical sidewall and a second sub-spacer on the first sub-spacer,
wherein the removing the upper portion of the lower spacer comprises recessing an uppermost surface of the first sub-spacer relative to the second sub-spacer to form a recess in the first sub-spacer between the vertical sidewall and the outer sidewall of the lower spacer, and
wherein the forming the upper spacer comprises forming the upper spacer on the vertical sidewall above the lower spacer to fill the recess.

6. The method of claim 1 , wherein the lower spacer is formed separately from the upper spacer.

7. The method of claim 1 , wherein the bottom-most surface of the upper spacer is above an uppermost surface of the lower spacer.

8. The method of claim 1 , wherein the lower spacer is not an air gap.

9. A method of forming a semiconductor memory device, the method comprising:
forming a bit line structure on a substrate;
forming a lower spacer covering a lower sidewall of the bit line structure, the lower spacer having a first thickness;
forming a storage node contact plug on the substrate at a side of the lower spacer, the storage node contact plug exposing an upper portion of the lower spacer;
removing the upper portion of the lower spacer using the storage node contact plug as a mask; and
forming an upper spacer on an upper sidewall of the bit line structure, the upper spacer having a second thickness that is less than the first thickness,
wherein the lower spacer comprises a first sub-spacer covering a vertical sidewall of the bit line structure and a second sub-spacer on the first sub-spacer, and
wherein the upper spacer extends in a vertical direction, and a bottom-most surface of the upper spacer is offset above an uppermost surface of the storage node contact plug, such that the bottom-most surface of the upper spacer does not abut the uppermost surface of the storage node contact plug.

10. The method of claim 9 , wherein the upper spacer is in direct contact with the first sub-spacer and spaced apart from the second sub-spacer.

11. The method of claim 9 , wherein the forming the upper spacer comprises:
conformally forming an upper spacer layer on an entire surface of the substrate;
forming a sacrificial spacer layer on the upper spacer layer; and
anisotropically etching the sacrificial spacer layer and the upper spacer layer to form a sacrificial spacer and the upper spacer and to expose an upper surface of the storage node contact plug.

12. The method of claim 11 , wherein the sacrificial spacer layer is formed of a material having an etch selectivity to the upper spacer layer.

13. The method of claim 11 , further comprising:
removing the sacrificial spacer to expose the upper spacer,
wherein the upper spacer covers both the first sub-spacer and the second sub-spacer.

14. The method of claim 13 , wherein the upper spacer has a first portion covering the upper sidewall of the bit line structure and a second portion protruding from a lower sidewall of the first portion to cover the first sub-spacer and the second sub-spacer.

15. The method of claim 9 , further comprising, before the forming the upper spacer:
removing an upper portion of the first sub-spacer to form a recess on the first sub-spacer,
wherein the upper spacer fills the recess.

16. A method of forming a semiconductor memory device, the method comprising:
forming a bit line structure on a substrate;
forming a lower spacer covering a lower sidewall of the bit line structure, the lower spacer having a first thickness;
forming a storage node contact plug on the substrate at a side of the lower spacer, the storage node contact plug exposing an upper portion of the lower spacer;
removing the upper portion of the lower spacer using the storage node contact plug as a mask; and
forming an upper spacer on an upper sidewall of the bit line structure, the upper spacer having a second thickness that is less than the first thickness,
wherein the lower spacer comprises a first sub-spacer, a second sub-spacer and a third sub-spacer sequentially covering a vertical sidewall of the bit line structure, and
wherein the upper spacer extends in a vertical direction, and a bottom-most surface of the upper spacer is offset above an uppermost surface of the storage node contact plug, such that the bottom-most surface of the upper spacer does not abut the uppermost surface of the storage node contact plug.

17. The method of claim 16 , further comprising, before the forming the bit line structure:
forming a recess by removing a portion of the substrate; and
forming a polysilicon pattern to fill the recess,
wherein the forming the bit line structure comprises etching the polysilicon pattern to form a bit line contact plug in the recess and to expose an inner sidewall of the recess, and
wherein the first sub-spacer covers the inner sidewall of the recess.

18. The method of claim 16 , wherein the first sub-spacer covers the upper sidewall of the bit line structure and the upper spacer covers a sidewall of the first sub-spacer and an upper

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Daeik
• Jang Semyeong
• Park Jemin
• Hwang Yoosang

Classifications

• H10W29/01

  Manufacture or treatment · CPC title

• H10W29/00

  Generic parts of integrated devices, not otherwise provided for · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title