Method of fabricating semiconductor device having contact structures

Patent metadata

Field	Value
Publication number	US-9543202-B2
Application number	US-201615060641-A
Country	US
Kind code	B2
Filing date	Mar 4, 2016
Priority date	Jun 15, 2015
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

Provided is a method of fabricating a semiconductor device, the method including forming interconnection structures extending parallel to each other on a substrate; performing a coating process and forming a liquid state silicon source material layer filling an area between the interconnection structures; performing a first annealing process, curing the liquid state silicon source material layer, and forming an amorphous silicon layer; and crystallizing the amorphous silicon layer and forming contact plugs.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming interconnection structures extending parallel to each other on a substrate;
performing a coating process and forming a liquid state silicon source material layer filling an area between the interconnection structures;
performing a first annealing process, curing the liquid state silicon source material layer, and forming an amorphous silicon layer; and
crystallizing the amorphous silicon layer and forming contact plugs.

2. The method as claimed in claim 1 , wherein the liquid state silicon source material layer includes a silane-based silicon material and a solvent.

3. The method as claimed in claim 2 , wherein the silane-based silicon material includes one or more of cyclopentasilane or neopentasilane.

4. The method as claimed in claim 2 , wherein the solvent includes one or more of toluene, cyclooctane, or ethanol.

5. The method as claimed in claim 1 , wherein the first annealing process is performed at a temperature of 350° C. or more for 30 to 360 seconds in a nitrogen atmosphere in which oxygen concentration is less than 1 ppm.

6. The method as claimed in claim 1 , further comprising performing a second annealing process, liquefying the amorphous silicon layer, and curing the liquefied amorphous silicon layer again.

7. The method as claimed in claim 6 , wherein the second annealing process includes a laser annealing process or a plasma annealing process.

8. The method as claimed in claim 1 , further comprising, after forming the amorphous silicon layer, performing an etch-back process to partially remove the amorphous silicon layer so that upper surfaces of the contact plugs are at lower levels than upper surfaces of the interconnection structures.

9. The method as claimed in claim 8 , further comprising:
performing a silicide process and forming silicide patterns on the contact plugs; and
forming contact patterns on the silicide patterns.

10. The method as claimed in claim 9 , wherein forming the contact patterns includes:
conformally forming a contact barrier layer on upper surfaces of the silicide patterns and sidewalls and upper surfaces of the interconnection structures;
forming a contact electrode layer on the contact barrier layer;
forming contact pattern isolation trenches partially passed through the contact barrier layer and the contact electrode layer; and
filling the contact pattern isolation trenches with a contact pattern isolation insulating material.

11. The method as claimed in claim 10 , wherein the contact pattern isolation insulating material includes silicon nitride.

12. The method as claimed in claim 1 , wherein the coating process includes a spin coating process or slot-die coating process.

13. A method of fabricating a semiconductor device, the method comprising:
forming a device isolation region defining an active region on a substrate;
forming gate structures intersecting the active region and extending parallel to each other in a first direction in the substrate;
forming interconnection structures extending parallel to each other in a second direction perpendicular to the first direction on a substrate;
forming an intermediate interlayer insulating layer filling an area between the interconnection structures that intersect the gate structures and a sacrificial layer filling an area between the interconnection structures that are between the gate structures;
removing the sacrificial layer and forming a contact hole exposing end portion of the active region;
performing a coating process and forming a liquid state silicon source material layer filling the contact hole;
performing a first annealing process, curing the liquid state silicon source material layer, and forming an amorphous silicon layer; and
crystallizing the amorphous silicon layer and forming a contact plug.

14. The method as claimed in claim 13 , wherein forming the intermediate interlayer insulating layer and the sacrificial layer includes:
forming the sacrificial layer filling all between the interconnection structures;
forming a mask pattern exposing the sacrificial layer between the interconnection structures that intersect the gate structures on the interconnection structures and the sacrificial layer;
removing the exposed sacrificial layer and forming a hole; and
forming the intermediate interlayer insulating layer filling the hole.

15. The method as claimed in claim 14 , wherein the intermediate interlayer insulating layer includes silicon nitride, and the sacrificial layer includes silicon oxide.

16. A method of fabricating a semiconductor device, the method comprising:
forming gate structures extending parallel to each other in a substrate;
forming interconnection structures intersecting the gate structures and extending parallel to each other on the substrate, the interconnection structures including first portions that do not intersect the gate structures and second portions that intersect the gate structures;
filling an area between the first portions of the interconnection structures with a silicon oxide layer;
filling an area between the second portions of the interconnection structures with a silicon nitride layer;
removing the silicon oxide layer between the first portions;
filling an area between the first portions of the interconnection structures on the substrate by performing a coating process using a liquid state silicon source material layer;
converting the liquid state silicon source material layer into an amorphous silicon layer;
forming amorphous silicon patterns having upper surfaces at lower levels than upper surfaces of the interconnection structures by partially removing the amorphous silicon layer; and
forming polysilicon patterns by crystallizing the amorphous silicon patterns.

17. The method as claimed in claim 16 , wherein:
the interconnection structures include interconnection contact patterns, interconnection barrier patterns, interconnection electrode patterns, and interconnection capping patterns stacked sequentially; and
upper surfaces of the amorphous silicon patterns are at higher levels than upper surfaces of the interconnection electrode patterns.

18. The method as claimed in claim 17 , further comprising, after forming the amorphous silicon patterns, forming holes between the interconnection structures by partially removing the amorphous silicon patterns in a thickness direction.

19. The method as claimed in claim 18 , further comprising forming spacers on inner sidewalls of the holes.

20. The method as claimed in claim 19 , wherein the spacers include silicon nitride, and in forming the spacers on inner sidewalls of the holes, the polysilicon patterns are formed by crystallizing the amorphous silicon patterns, and contact plugs including polysilicon are formed.

Assignees

• Samsung Electronics Co Ltd

Inventors

• KOO Jamin
• Kim Youngseok
• Lee Kongsoo
• Bae Goeun

Classifications

• H10D64/01306

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title

• H10P14/46 Primary

  using a liquid · CPC title

• H10W20/4451

  Semiconductor materials, e.g. polysilicon · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title